For very large multiplexers in FPGAs, there will be a huge propagation delay that may create a critical path and cause timing violation.
Therefore, one possibility I assume is to use multicycle path for very large multiplexers in FPGA.
Another possibility according to https://www.doulos.com/knowhow/fpga/multiplexer/ is to pipeline the multiplexer.
What does it mean to pipeline the multiplexer since it is just a combinatorial block anyway? Merely registering the input and output will not be enough I assume.
you can pipeline pretty much anything - why would a multiplexor be any different?
Yes, its a combinatorial thing at a basic level, but what about 8 to 1 made out of 7 2-1 muxes with registers at all input/outputs?