what does hold time check mean in Design Compiler?

Hi, I have a question concerning synthesis in ASIC flow.

For Design Compiler, we introduce two terms which is Request time(RT) and Arrive Time(AT), and when we add timing constraint we always expect the positive slack which follow the equation.

Slack = RT - AT;

But I read a book and it is said that" For setup time check, we always check RT - AT, but for hold time check, we check AT - RT."
I cannot quite follow the words above. Or I don't have much experience about synthesis and never meet question concerning hold time check, can someone explain the hold time with more details or give a example?

I only know in theory if a circuit cannot meet hold time would clock new data instead of old data on previous stage which means too fast.

Thanks

Here's a basic explanation of set up time and hold time with a graph.
http://referencedesigner.com/tutorials/si/si_02.php
Poorly stated in book.