what determine the supply voltage of a cmos ic chip?

[catrat]

hi, friends,
I was asked to help design a small mixed-mode cmos IC chip. the supply voltage of target chip is about 1.8V to 5V. I know nothing about the cmos process,only design some digital logic before. what affect the input voltage range ? the process(0.35 0.25 0.18)? the IO pad design? thanks a lot!

regards,

 

[dick_freebird]

Gate ox and channel length and some "drain engineering"
account for transistors' working voltage. Some are hard
limits, some are negotiable against environment and reliability.
If you want a natural 5V capability without worrying, you are
probably at a 0.8um drawn gate and at least 120A Tox (if
you want reliable). You can probably find some 0.5um
range technologies where the "I/O" transistors have a thick
oxide and relaxed groundrules so you can get some latitude
in density and working voltage, section by section. By the
time you get down to 0.18um you'll be lucky to have 3.3V
as your high voltage option.

 

[catrat]

thanks for the reply.
now current mcu chips on market, for example, atmel's avr series, all support a wide power supply voltage range from 1.8v to 5.5v. How does it make this? with low voltage logic and circuit inside and a wide voltage range tolerant io pad design? and it should have some voltage regulator built in?

 

[erikl]

... support a wide power supply voltage range from 1.8v to 5.5v. How does it make this? with low voltage logic and circuit inside and a wide voltage range tolerant io pad design?

3 different oxide thicknesses for 3 different voltage regions (e.g. 1.8V for the digital core, 3.3V for ADC and other analog stuff, and 5V for the IOs). At least 2 additional masks per oxide thickness are needed (active_area & contacts), which means (at least) 4 more masks in the mask set in comparison to a 1-voltage-only-design. Apart from the additional mask costs and process work steps, these are "yield-critical" masks, rendering the process even more expensive because of decreasing its yield.

... and it should have some voltage regulator built in?

For sure! Sometimes the 5V IOs are only 5V-tolerant, i.e. the chip is operated with (nominal) 3.3V (or 2.5V), and the core voltage of 1.8V (or 1.2V) is generated internally.

 

[FvM]

You did only consider technology dependent maximum transistor voltage. Apart from maximum voltage, there's another
important parameter: MOS threshold voltage. It can be varied in transistor design and also decides about the voltage range
and speed versus voltage of a CMOS desígn. You'll surely figure out, that it must have a certain relation to the supply
voltage for intended operation of a CMOS circuit.

 

[erikl]

... must have a certain relation to the supply voltage for intended operation of a CMOS circuit.

Fortunately, Vth rises with TOX. But of course you're right: if special Vth adjustment is required, additional implants (and 2 more implant masks, for nmos & pmos) are necessary, too. (That's why I wrote "at least 2".) ;-)

 

[catrat]

the chip, is about a mcu plus a op amp and voltage comparator,the power supply of the chip, is 1.8v to 5.5v, and the digital io voltage is related to the power supply, and the input of op amp is about 0 to 500mv ... and the mcu should have flash memory built in. so first of all, I should choose a process with mixed-mode and flash mem support, right? and 2nd, the process, ( .18 .25 or .35) should based on the low voltage of power supply (1.8v), right? how about running all in a low voltage inside the chip and with a on-chip voltage regulator on power supply pin?

 

[erikl]

... so first of all, I should choose a process with mixed-mode and flash mem support, right?

For sure!

... and 2nd, the process, ( .18 .25 or .35) should based on the low voltage of power supply (1.8v), right?

Right. Probably a .18 process.

how about running all in a low voltage inside the chip and with a on-chip voltage regulator on power supply pin?

May be possible. But it depends also on which supply voltage the flash mem will run, and which analog building blocks for which operating voltage are already available.

 

[deepak242003]

3 different oxide thicknesses for 3 different voltage regions (e.g. 1.8V for the digital core, 3.3V for ADC and other analog stuff, and 5V for the IOs). At least 2 additional masks per oxide thickness are needed (active_area & contacts), which means (at least) 4 more masks in the mask set in comparison to a 1-voltage-only-design.

Can you elaborate your point?.

My understanding there should be only one extra mask layer ( thick oxide layer) for corresponding voltage range.. Contact and diffusion will be same.. That leads to only 2 more mask for 3 differnt voltage regions..

Please correct if I am mistaken anywhere.

Deepak.

 

[erikl]

My understanding there should be only one extra mask layer ( thick oxide layer) for corresponding voltage range.. Contact and diffusion will be same.. That leads to only 2 more mask for 3 differnt voltage regions..
Deepak.

Hi Deepak,
may be this depends on the foundry (and on the process size) : our fab uses a special contact mask for each oxide thickness, at least for processes ≤ 0.35µm. AFAIK, the reason for this is the amount of underetching: the thicker the oxide is, the more underetching occurs. That's why the contact dimensions are prepared differently during data prep. For design, the contact dimensions are all the same, of course. And, yes: diffusion mask is the same.
Rgds, erikl

 

[deepak242003]

Does it mean that, although we are using same diffusion and contact for every oxide thickness, while fabrication contact mask are different....??

Deepak.

 

[erikl]

Does it mean that, although we are using same diffusion and contact for every oxide thickness, fabrication contact masks are different....??
Deepak.

Exactly!
erikl