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[SOLVED] What could be the reason for VCC and ground being optimized away ?

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blooz

blooz

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Mapping report Report says that

Section 4 - Removed Logic Summary
---------------------------------
2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC

full report

Code: 
Release 12.1 Map M.53d (nt)
Xilinx Mapping Report File for Design 'alu'

Design Information
------------------
Command Line   : map -intstyle ise -p xc3s400-pq208-5 -cm area -ir off -pr off
-c 100 -o alu_map.ncd alu.ngd alu.pcf 
Target Device  : xc3s400
Target Package : pq208
Target Speed   : -5
Mapper Version : spartan3 -- $Revision: 1.52 $
Mapped Date    : Wed Mar 16 20:34:17 2011

Design Summary
--------------
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of 4 input LUTs:                69 out of   7,168    1%
Logic Distribution:
  Number of occupied Slices:             37 out of   3,584    1%
    Number of Slices containing only related logic:      37 out of      37 100%
    Number of Slices containing unrelated logic:          0 out of      37   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:          69 out of   7,168    1%
  Number of bonded IOBs:                 31 out of     141   21%

Average Fanout of Non-Clock Nets:                3.05

Peak Memory Usage:  145 MB
Total REAL time to MAP completion:  3 secs 
Total CPU time to MAP completion:   3 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

Section 6 - IOB Properties
--------------------------

+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard          | Diff  | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |                      | Term  | Strength | Rate |              |          | Delay    |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| a<0>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| a<1>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| a<2>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| a<3>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| a<4>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| a<5>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| a<6>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| a<7>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| b<0>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| b<1>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| b<2>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| b<3>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| b<4>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| b<5>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| b<6>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| b<7>                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| cin                                | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| cout                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| op<0>                              | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| op<1>                              | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| op<2>                              | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| op<3>                              | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| y<0>                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| y<1>                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| y<2>                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| y<3>                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| y<4>                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| y<5>                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| y<6>                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| y<7>                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| zout                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Timing Report
--------------------------
This design was not run using timing mode.

Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 12 - Control Set Information
------------------------------------
No control set information for this architecture.

Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
Here is the Schematic
View attachment upload.pdfView attachment upload.pdf
 
Last edited:

The question you should ask yourself is "why not?". These nets are a candidate for optimization, you have optimization enabled, so in this case they are optimized away.

Does the logic not operate as you specified?
 
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    blooz

    blooz

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The Post Translate Simulation Works Fine .Confused about that unconnected connected components and optimized parts
 

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