modelsim errors
looks like all of the errors are syntax errors. but im really sorry i dont know VHDL so i cant help but i will try.
the error that says "Case statement only covers 16 out of 6561 cases" is telling you that you didnt cover all the possible combinations of the variables. this usually results in synthesis of latches which gives problems in static timing analysis. you should always define some action for all possible cases or write a default statement that tells what to do when except for the mentioned cases.
the identifier op2 might not have been declared before it is being used. so that would be a simple error to remove.
the error on line 129 might be because of an assignment of a variable of one data type to a variable of another data type.
please refer to some VHDL book like "Circuit design with VHDL" (available for download at edaboard) for these errors