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What causes Modelsim errors and how to fix them?

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salma ali bakr

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hi, is there a way to know about modelsim errors...what caused them and how to fix them....thanks....Salma
 

Matrix_YL

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modelsim errors

of course, there have a way fix errors ,pls see compile report in MOdelSim
 

samcheetah

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Re: modelsim errors

it depends on the errors. it might be that your code isnt write and modelsim is giving you syntax errors. or it might be that modelsim wasnt installed properly or there are some corrupt files.

can you show a screenshot of the error?
 

salma ali bakr

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Re: modelsim errors

thanks for replying....i know that comes in the report but i don't know what caused it and how to fix it...

it is errors like:

# ERROR: D:/VHDLmodelsim/up1.vhd(105): Unknown identifier: op2
# ERROR: D:/VHDLmodelsim/up1.vhd(120): No feasible entries for infix op: "sll"
# ERROR: D:/VHDLmodelsim/up1.vhd(129): Bad right hand side in assignment.
# ERROR: D:/VHDLmodelsim/up1.vhd(102): Case statement only covers 16 out of 6561 cases.


should some libraries be included maybe, i guess the last one can be solved by putting others....i am new to vhdl actually:)

thanks in advance...

Salma
 

samcheetah

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modelsim errors

looks like all of the errors are syntax errors. but im really sorry i dont know VHDL so i cant help but i will try.

the error that says "Case statement only covers 16 out of 6561 cases" is telling you that you didnt cover all the possible combinations of the variables. this usually results in synthesis of latches which gives problems in static timing analysis. you should always define some action for all possible cases or write a default statement that tells what to do when except for the mentioned cases.

the identifier op2 might not have been declared before it is being used. so that would be a simple error to remove.

the error on line 129 might be because of an assignment of a variable of one data type to a variable of another data type.

please refer to some VHDL book like "Circuit design with VHDL" (available for download at edaboard) for these errors
 

ikru26

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Re: modelsim errors

buddyyyy..its syntax error
 

salma ali bakr

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Re: modelsim errors

thanks guys....i fixed the errors a few days ago...guess i should be more careful about my syntax....but i have some problems now in how to implement the PC for the up i am writing....it just doesn't increment and isn't realized as a signal except in a process....dunno what to do....NOTE: i am writing the up as behavioral...something like a Von Neumann processor but all on RAM only, any advice :)
 

echo47

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modelsim errors

If you can show us a small self-contained piece of code that demonstrates the problem, someone here can probably help you debug it. Please don't upload a large complex project.
 

nee_naresh04

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Re: modelsim errors

# ERROR: D:/VHDLmodelsim/up1.vhd(105): Unknown identifier: op2
# ERROR: D:/VHDLmodelsim/up1.vhd(120): No feasible entries for infix op: "sll"
# ERROR: D:/VHDLmodelsim/up1.vhd(129): Bad right hand side in assignment.
# ERROR: D:/VHDLmodelsim/up1.vhd(102): Case statement only covers 16 out of 6561 cases.


if u compile ur code then u will see one compalation report...if u find any error like above then .read patently and double clik on the each error then u will go to ur code where u did that mistake...
 

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