What are the things to keep in mind when assignning pins in CPLD before actu aldesign

[vsheladiya]

Hi all,

I need to give CPLDs pin assignments to the system design group before designing it actually.

can anybody help me which type of things i should keep in mind at the time of pin assignment? Or I can assign it randomly?

Thanks in advance.

 

[SkyHigh]

Look out for:
1. Power, Output or Input (can be latched or passive), Bi-direction In & Out (usually for data bus to Read & Write)
2. 3.3V (maybe 2.5V and 1.8V, if available in CPLD. FPGA usually has).
3. I know some CPLDs give you the option to use Tri-State, Open-Drain and even Schmitt-Trigger. Default is CMOS drive.

Depending brand and series of CPLD you use, you may have slight varying options, but usually the basic pin I/O are the standard ones.

 

[vsheladiya]

otherthan this what about timing? Is there any effect of pin assignment on design timing or placement?

 

[SkyHigh]

Timing and placement has nothing to do with pin assignment.

Timing (rise and fall time) is determined by the load (e.g. fan in and fan out) and the buffer I/O (standard driver in the CPLD that you cannot change).

You ought to be more concerned about grouping functional signals (addr, data, r/w, reset, enable, select, etc) in your design to improve performance like signal integrity, EMI and ease of PCB placement.

 

[vsheladiya]

i am not talking about Timing of rise and fall time, i am asking for set up and hold time requirement. will it be affected by the pin placement?

 

[SkyHigh]

Then you should be more SPECIFIC by asking for Timing Violation because when you said Timing, it is a very broad topic.

When it comes to Setup and Hold time violation and requirement, you should be concerned about your VLSI, if not ASIC design, by checking Static Timing Analysis thoroughly.
And you better make sure your test vectors have all these verified.

Pin placement has nothing to do with setup and hold time. It is the logic (if any glitches or race conditions), critical path, domain clock (jitter if any, depending your clock layout) that you implement in your VLSI (or ASIC) that determine if you violate setup and hold.

In CPLD, you can only improve your algorithmic design (behavioural or structural) to improve setup and hold time. You cannot control anything else.