Because I have a block which has 2 sub-modules , 1 of them is placed and routed module and the other is just a RTL module. So when I try to run the block as whole, it reports that it doesn't understand tranif constructs.
Because I have a block which has 2 sub-modules , 1 of them is placed and routed module and the other is just a RTL module. So when I try to run the block as whole, it reports that it doesn't understand tranif constructs.
I don't see anything such , even though my block is wrong , My question is plain and simple, Are there any constructs in Tetramax that can be substituted in place of tranif0 and tranif1?
You cannot substitute r/tran/0/1 primitives with buf/1/0 or anything else without knowing the context of their usage. All of the tran primitives provide bi-directional flow of signals
It is not possible to model the full behavior of a tranif1/0 primitive within the Verilog language itself. And I'm not sure if the VPI gives you the capability to resolve the wires involved in C code. And even if you could, that would not solve the problem you mention in your previous post - the down stream tool would not recognize the C code you wrote.
What you need to do is look at the larger context and try to replace the functionality around it.
Because I have a block which has 2 sub-modules , 1 of them is placed and routed module and the other is just a RTL module. So when I try to run the block as whole, it reports that it doesn't understand tranif constructs.
Is seems to me the problem is they should have synthesized the RTL module so that it has the correct library primitives instead of using the RTL directly along with the placed and routed netlist module. But perhaps this is not the way the tools work now days.