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what are the steps for building good and robust clock tree.

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frequency, rise time, fall time

This is a very generic and a wide question. Most of the time once you have completed the initial placement, then based the following the cts tool will build a good robust clock tree

1. design constraints (SDC)
This will contain the basic clock definations, false_paths, multi-cycle paths, transition time etc ..
2. Clock tree rule (clock net spacing and width rule and max cap on nets)
3. Clock skew groups
Most of the tools will derive the skew groups from the sdc. However you can also create custom skew groups as per you design.
Custom skew groups are mainly need to if you know there are a bunch of flops that need a delayed/early clock so as to fix hold/setup time (you really need to know your design).
4. which specific clock cells are to be used

Once the clock tree has been synthesized then you can ask the tool to optimize the clock tree for fixing the setup/hold time, DRV, SI, clock skew.

Hope this helps.


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