Re: need ICT requirements?
Design-for-Testability Rules
These rules summarize good design-for-testability practices.
¨ Do not plate tooling holes.
¨ Datum zero is one of the tooling holes.
¨ Do not use less than two 0.125-inch diameter tooling holes at opposite ends of the UUT.
¨ The minimum pad size is 0.050 inches.
¨ The minimum test pad clearance is 0.02 inches.
¨ Probe leaded components.
¨ Leads should not exceed 0.060 inches.
¨ All nodes must have one point of access. Notify the test engineer if this is not possible.
¨ Do not tie inputs directly to ground or Vcc. Use isolated pull-up resistors.
¨ Solder or silkscreen all vias.
¨ Test pad node numbers on a schematic should represent the page of the schematic on which the test pad is located.
¨ Provide multiple power and ground test points.
The phrase "design-for-testability" refers to the on-going effort by both component and board designers to improve the observation and control of their designs during test.