Jul 15, 2008 #1 S S.Nikhil Member level 1 Joined Oct 9, 2007 Messages 34 Helped 18 Reputation 36 Reaction score 17 Trophy points 1,288 Activity points 1,553 Hi, What are the factors that determine the setup time of a flip-flop. According to me, it is the input transition and slew. Let me know If I am correct. thx S. Nikhil
Hi, What are the factors that determine the setup time of a flip-flop. According to me, it is the input transition and slew. Let me know If I am correct. thx S. Nikhil
Jul 15, 2008 #2 gliss Advanced Member level 2 Joined Apr 22, 2005 Messages 691 Helped 75 Reputation 150 Reaction score 16 Trophy points 1,298 Activity points 5,892 Re: Flop setup time The setup time is determined by the cell provider. The timing information is extracted from the technology information and the cell layout. The input transition and slew affect the delays.
Re: Flop setup time The setup time is determined by the cell provider. The timing information is extracted from the technology information and the cell layout. The input transition and slew affect the delays.
Jul 17, 2008 #3 M MarcS Member level 4 Joined Jun 30, 2008 Messages 79 Helped 52 Reputation 104 Reaction score 46 Trophy points 1,298 Activity points 2,036 Re: Flop setup time Gliss is correct
Jul 17, 2008 #4 H hfooo1 Member level 1 Joined Nov 3, 2007 Messages 37 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,492 Flop setup time you can check std.lib look for the factor in the lookuptable
Jul 17, 2008 #5 R red_boy0928 Newbie level 6 Joined May 30, 2008 Messages 11 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,324 Re: Flop setup time setup time is dertimed by the transistion of clock signal and data signal. Added after 2 minutes: Just suppplement, for a certain DFF cell, larger transistion of clock signal and data signal, larger setup time.
Re: Flop setup time setup time is dertimed by the transistion of clock signal and data signal. Added after 2 minutes: Just suppplement, for a certain DFF cell, larger transistion of clock signal and data signal, larger setup time.
Jul 17, 2008 #6 E ericyuan Member level 1 Joined Mar 8, 2006 Messages 36 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Activity points 1,441 Flop setup time the DFF setup time is [delay CK->close latch gate] - [delay D->close latch source]