cpldfit jed
Check Appendix A again. JED files are created by the CPLDfit utility which is for CPLDs, not FPGAs.
It's true that Appendix A doesn't specifically say that bit files are for FPGA, and it neglects to mention bin files. Xilinx likes to scatter useful info throughout its documentation. See page 309 of the Development System Reference Guide for a little more info about bit and bin bitstream files.
You can download either bit or bin files through JTAG directly to Spartan or other Xilinx FPGA devices. I've written a small JTAG utility that does exactly that, using a parallel port interface. (I wrote it for a company, so sorry I can't share it.) You will need to issue the correct JTAG commands so the FPGA will accept your bitstream data. The command sequence is described (but perhaps not thoroughly) in the Configuration User Guide for your FPGA type. To find the correct chapter, search the manual for the word JPROGRAM.
Sometimes I use iMPACT to generate a SVF file (a sequence of JTAG commands and responses), and then study that file to better understand the sequence required by a particular FPGA operation. Your program could parse and execute a suitable SVF file to configure the FPGA.
I prefer to use bin files, even though the FPGA will ignore the header at the beginning of the bit file.
Do you mean Spartan, or Spartan-II, or Spartan-3?
Here's the Spartan-3 Generation Configuration User Guide. The JTAG programming info begins in Chapter 9, page 187:
https://www.xilinx.com/support/documentation/user_guides/ug332.pdf