Jul 9, 2008 #1 A ASIC_intl Banned Joined Jan 18, 2008 Messages 260 Helped 2 Reputation 4 Reaction score 2 Trophy points 1,298 Activity points 0 What are all the differences between signal assignments and variable assignments in VHDL?
Jul 9, 2008 #2 M mahdieh79 Newbie level 6 Joined Oct 31, 2007 Messages 13 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,348 Re: VHDL Hi <= is for signal assignment, but := is for variable assignment.
Jul 10, 2008 #3 H himadrisinghraghav Newbie level 3 Joined Aug 9, 2007 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,297 Re: VHDL variable assignment cause variables to get their values instantaneously, while signal assignment always cause signals to get their values at a later time (atleast a delta delay)
Re: VHDL variable assignment cause variables to get their values instantaneously, while signal assignment always cause signals to get their values at a later time (atleast a delta delay)