Perhaps it makes sense first to clarify what you really mean as the phrase "digital PLL" is used in several ways. Some people mean only a digital PD/PFD and some other really mean "complete digital" (including filter and a number controlled oscillator)
it is a path to preserve system performance in the presence of NONscaling
Analog does not profit in general from further scaling but price and SOC aspects contrain analog to search for alternatives.
Digital PLL is one!
But VCO is analog, beside digital driven. The missing part is the high resolution phase detector. Analog phase detectors could easy resolve 200fs-1ps of a 20ns reference clock. The effort to built an 200fs resolving, 20ns range TDC is higher than everything else.
So a litle digital here and there to avoid NONscaling analog issues!
I was looking for a paper that proves these numbers. Unfortunately, it's easy to find PFD resolutions for TDCs but not for analog PDFs. Anyone can suggest me a paper? Thanks