what are IODelays in Xilinx FPGAs

[syedshan]

Dear all,

I cannot understand completely the concept of IODelay (what is tap delay) .
How can they effect the operation of the system?
Does they only matter when we are using ADC?
Do we have signal loss or signal quality loss because of them?

Bests,
Shan

 

[shahulakthar]

Check this link
https://www.alteraforum.com/forum/showthread.php?t=37974

 

[ads_ee]

Check this link
https://www.alteraforum.com/forum/showthread.php?t=37974

shhulakthar I think you misunderstood the OPs question, which wasn't about Altera or I/O delay.

Xilinx has an element called IODELAY, which allows for inserting a delay between 0-31 taps for V6 into the signal passing through the input or output. There is a reference clock, which is nominally 200 MHz, that is used by the IDELAYCTRL to set a time reference for calibrating the IODELAY modules in the same region. You can basically think of the taps as the connections between a daisy chain of delay elements, therefore the signal goes into the first delay and gets delayed by n-taps at 78ps per tap. Using this you can adjust the phase relationship of a signal with its peers on a pin by pin basis.