What are internal setup and external setup times?

[matrixofdynamism]

While I understand the concept of setup and hold times for register to register transfers in a synchronous design, I have come across terms "internal" and "external" related to each of these. What is the difference between internal setup time & exernal setup time and, internal hold time and external hold time? Which of these is intrinsic to the circuit as it is built on silicon and which is influenced by how a chip is used and connected to other componenets on the circuit board?

 

[artmalik]

I think these terms "internal" and "external" might just be nomenclature used by the person who has written the document. I think you are clear on the register to register timing(setup/hold). These have to be met using .libs that have been used for the timing. The issue of "internal/external" comes when two independent blocks are interacting with the same clock or different clock. Here cross domain crossing rules are used. If there is "some" synchronization between the clocks (if they come from same source) then the setup/hold time has to sufficed at the block level. most of the time they are done using cells called synchronizers and if there are multiple chips are used then there clock recovery circuits, asynchronous protocols are used.

 

[D.A.(Tony)Stewart]

I think it only refers to where the bus is located , internal or external to the uC, CPU or GPU chip for example.

It also has significance in reducing setup times for cell-based production and lean manufacturing, where setup refers to processes inside the cell our outside.