asch1hazshortj.pdf
A glitch happens sometimes as signals propagate through combinational logic.
Before reaching the final steady state value, sometimes, a wrong intermediate value shows up at the output during the settling phase. This is called a glitch.
The reason why it happens is because of the different signal paths have different delays. So when one input reaches the input of a gate while the other input is delayed, the wrong output may occur. The output signal will be corrected once all of the correct input has propagated through.
I've attached a simple diagram.
In the picture below, because of the inverter delay, the AND gate sees both of its input high for a short time. This is when the glitch happens.
for a more detailed description, see below:
**broken link removed**
Good luck!