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A glitch happens sometimes as signals propagate through combinational logic.
Before reaching the final steady state value, sometimes, a wrong intermediate value shows up at the output during the settling phase. This is called a glitch.
The reason why it happens is because of the different signal paths have different delays. So when one input reaches the input of a gate while the other input is delayed, the wrong output may occur. The output signal will be corrected once all of the correct input has propagated through.
I've attached a simple diagram.
In the picture below, because of the inverter delay, the AND gate sees both of its input high for a short time. This is when the glitch happens.
Suppose you have a combinational logic and if assume having a unit gate delay for each of them, and if the path taken from input to output say, 1st path is having 2 gates and 2nd path is having 2 gates, and if the inputs is given to it, then definitely because of an additional gate in the second path, there exists a glitch in the circuit.
But if you consider the gate has zero delay(unrealistic), then the problem of glitches does not exit