Re: Schematic V/S HDL
Typically, most CPLDs are large fan-in AND gates and a small number of flops. If you purposely structure your schematic, you can force more logic into a CPLD with schematic than with HDL. However, if you do not generate your schematic with the topology of the CPLD in mind, then it will be interpreted just like the HDL and you are at the mercy of the compiler.
In general, HDL is the way to go for future designs. This is because most vendors are scaling back support for schematic. The compiler is continually being improved for HDL, which the schematic end often only get major bug fixes.
You can always have the best of both worlds, since you can instantiate logic primitives within your HDL code. Therefore, you can call primitives that exactly match how you would wire it up in a schematic.
---- Steve
Added after 32 seconds:
Typically, most CPLDs are large fan-in AND gates and a small number of flops. If you purposely structure your schematic, you can force more logic into a CPLD with schematic than with HDL. However, if you do not generate your schematic with the topology of the CPLD in mind, then it will be interpreted just like the HDL and you are at the mercy of the compiler.
In general, HDL is the way to go for future designs. This is because most vendors are scaling back support for schematic. The compiler is continually being improved for HDL, which the schematic end often only get major bug fixes.
You can always have the best of both worlds, since you can instantiate logic primitives within your HDL code. Therefore, you can call primitives that exactly match how you would wire it up in a schematic.
---- Steve