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What are advantages and disadvantage of using schematics over HDL coding?

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alexz

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What are advantages and disadvantage of using schematics over HDL coding (in particular VHDL) and opposite for designing CPLD devices ?
 

banjo

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Re: Schematic V/S HDL

Typically, most CPLDs are large fan-in AND gates and a small number of flops. If you purposely structure your schematic, you can force more logic into a CPLD with schematic than with HDL. However, if you do not generate your schematic with the topology of the CPLD in mind, then it will be interpreted just like the HDL and you are at the mercy of the compiler.
In general, HDL is the way to go for future designs. This is because most vendors are scaling back support for schematic. The compiler is continually being improved for HDL, which the schematic end often only get major bug fixes.

You can always have the best of both worlds, since you can instantiate logic primitives within your HDL code. Therefore, you can call primitives that exactly match how you would wire it up in a schematic.

---- Steve

Added after 32 seconds:


Typically, most CPLDs are large fan-in AND gates and a small number of flops. If you purposely structure your schematic, you can force more logic into a CPLD with schematic than with HDL. However, if you do not generate your schematic with the topology of the CPLD in mind, then it will be interpreted just like the HDL and you are at the mercy of the compiler.
In general, HDL is the way to go for future designs. This is because most vendors are scaling back support for schematic. The compiler is continually being improved for HDL, which the schematic end often only get major bug fixes.

You can always have the best of both worlds, since you can instantiate logic primitives within your HDL code. Therefore, you can call primitives that exactly match how you would wire it up in a schematic.

---- Steve
 

gliss

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Schematic V/S HDL

HDL is the way to go.
 

alexz

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Re: Schematic V/S HDL

gliss said:
HDL is the way to go.
Why?

I am coming from the point of view that to draw schematics is quicker then writing code. Because when you write a code, you have to imagine the schematics anyway don't you?
 

jetset

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Re: Schematic V/S HDL

I use a combination of both, I make separate VHDL modules, and then I put it all togheter by means of a schematics tool. Or if a module is a simple circuit I do it instantly by schematic.
 

Iouri

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Schematic V/S HDL

portability.. How you can transffer schematic between Altera and Xilinx or to get it into the Modelsim
 

alexz

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Re: Schematic V/S HDL

Iouri said:
portability.. How you can transffer schematic between @ltera and Xilinx or to get it into the Modelsim
Yes, that is a disadvantage of using schematics.
anything else?
 

gliss

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Re: Schematic V/S HDL

- Become as good as you can with HDL because that is the future. Companies and schools are migrating away from schematics for the most part.
- Easier to design and maintain. Going back and looking at properly written HDL code is with comments is much easier than trying to decipher a schemtic.
- HDL compilers are good and getting better all the time.
- Once a design becomes larger than a few hundred gates I would say schematics are out of the question. Who has the time.
- Portability, but that's already been said.

I'm not saying schematics are going to disappear. There will be a place for them for quite some time. But for new engineers and new designs, don't even bother with schematics, they'll hold you back.
 

echo47

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Schematic V/S HDL

Ten years ago, I used schematic capture with Xilinx 4000-series FPGAs. That was tedious work! When HDL tools became available a few years later, I tought myself Verilog and within a week I was designing stuff ten times faster than before. I've never once looked back.
 

sp

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Schematic V/S HDL

think bout when u are connecting thousand n thousand of pins together in sch... HDL would b much more easy....

emm.. how bout finite state machine... like wad echo47 mentioned.. it is very tendious work... use HDL... and it ease all the task...

regards,
sp
 

drp

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Re: Schematic V/S HDL

is there any vhdl to sch "block modules" translator ?. I mean , separating vhdl in modules an just click and "watch" somekind a sch of modules and interconexion between them ? (just as informative sch, not needed architecture of the modules).
 

echo47

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Schematic V/S HDL

After I compile an HDL project with Xilinx ISE, I can run "View RTL Schematic" to see a diagram of the synthesized logic. It's sprawling and messy, but sometimes useful. Synplify has a similar feature.
 

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