Taher_Selim
Member level 5
Hallo,
I have simulated the following code using ModelSim.
I got weird results. I expect data_out_stb to be raised at next clk cycle after (readReq='1') but as you can see in the simulation wave, it is raised at the same clock edge. does anyone has explanation for that
To understand why it is weird, I modified the code to be
the "data_in_ack <= '1';" is updated in next clk cycle as shown in photo 02
I have simulated the following code using ModelSim.
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fifo_SCnt is
generic(
RAMsize: integer := 256;
DataWidth: integer := 8
);
port(
clk: in std_logic;
rst: in std_logic;
data_in: in std_logic_vector (DataWidth-1 downto 0);
data_out: out std_logic_vector(DataWidth-1 downto 0);
readReq: in std_logic;
writeReq: in std_logic;
data_in_ack: out std_logic;
data_out_stb: out std_logic;
empty: out std_logic;
full: out std_logic
);
end entity;
architecture rtl of fifo_SCnt is
type memory_type is array (0 to RAMsize-1) of std_logic_vector(DataWidth-1 downto 0);
signal memory : memory_type :=(others => (others => '0'));
signal read_ptr : integer range 0 to RAMsize-1 :=0;
signal write_ptr : integer range 0 to RAMsize-1 :=0;
signal isFull : std_logic;
signal isEmpty : std_logic;
signal writereq_cnt: integer := 0;
signal readreq_cnt: integer := 0;
begin
process (clk, rst)
begin
clk_rst : if (rst = '1') then
memory <= (others => (others => '0'));
empty <='1';
isEmpty <= '1';
full <='0';
isFull <= '0';
data_out <= (others => '0');
data_out_stb <= '0';
data_in_ack <= '0';
read_ptr <= 0;
write_ptr <= 0;
elsif (clk'event and clk='1') then
memory(write_ptr+1)<=X"65";
if(write_ptr < RAMsize-1) then
write_ptr <= write_ptr+1;
else
write_ptr <= 0;
end if;
if (readReq='1') then
data_out <= memory(read_ptr+1);
data_out_stb <= '1';
full <= '0';
isFull <= '0';
end if;
end if clk_rst;
end process;
end rtl;
I got weird results. I expect data_out_stb to be raised at next clk cycle after (readReq='1') but as you can see in the simulation wave, it is raised at the same clock edge. does anyone has explanation for that
To understand why it is weird, I modified the code to be
Code:
elsif (clk'event and clk='1') then
if (readReq='1') then
data_out <= memory(read_ptr+1);
data_out_stb <= '1';
full <= '0';
isFull <= '0';
data_in_ack <= '0';
end if;
if (writeReq='1') then
memory(read_ptr+1) <= data_in;
data_in_ack <= '1';
empty <= '0';
isEmpty <= '0';
if(write_ptr < RAMsize-1) then
write_ptr <= write_ptr+1;
else
write_ptr <= 0;
end if;
end if;
end if clk_rst;
the "data_in_ack <= '1';" is updated in next clk cycle as shown in photo 02
Last edited: