sjamil02
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Hi All,
When I simulated the loop gain and phase margin (See attached schem for sim setup), the simulation results look's strange.
.............
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In other words, the regulator operation depends on the ability of the output transistor to short a 100 mohm source. Can it? It's only W=6µ.Another question, is it correct to model the power supply input current in my schematic? I put a dc source (Vdd=1V) with a series resistor (100mOhm --> package+ball resistance).
Please refer to the attached block sim setup.The phase margin is determined at a frequency with loop gain=0 dB. This point cannot be identified in your graph. However, I cannot comment to your simulation setup since it is still very hard to detect. Please try to create a block diagram
I am not familiar with loop gain simulation alternatives. Can you please guide me on the steps to do this in cadence? Any reference materials or link will be helpful too.Opening the loop for injection of a test signal destroys the operatiing point. There are specific procedures to circumvent such problems. Are you familiar with loop gain simulation alternatives?
The shunt transistor size is 6um/0.3um <56:1> = 336um/0.3um.In other words, the regulator operation depends on the ability of the output transistor to short a 100 mohm source. Can it? It's only W=6µ.
I used 1mH inductor and 100uF capacitor and injected AC test signal for loop gain measurement. This is the only method that i am familiar with. Please suggest a better ways.I don't see an AC source to set up a gain measurement. Where is it?
P.S.: is there really a 1m/100u LC low-pass in the loop? Driven by a 10k node? What it's good for?
Still, I can't understand the LF -100dB result.
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