way is known by verilog AMS ....

[Muthuraja.M]

Hi all,

i want to know about the verilog AMS language ?

How it is used to describe the analog and mixed signals.

Is it possible to use that language in modelsim software or there is a separate software is available ?

pls tell me how to use the verilog AMS language.

Thanks in advance ...

 

[vardan]

Hi,
There is a Verilog (in the context it may be referred as Verilog-D) to model digital processes, there is Verilog-A to model analog processes. Verilog-AMS allows modeling both analog and digital processes in the same module. You can consider that Verilog-D and Verilog-A are subsets of Verilog-AMS.
I am inclined to think ModelSim won't simulate Verilog-AMS code. Search their website.
Usually, there should be two simulators involved: digital and analog, like VCS and HSIM.

To use Verilog-AMS language I would suggest first reading a textbook on Verilog-A/AMS (The Designer's Guide to Verilog-AMS is quite good), walk through examples. Next, you should invest some time to understand tools setups for cosimulation, like selecting analog simulator, setting interfaces between digital and analog, handling ports mismatches, etc.
If you know SPICE and Verilog, Verilog-AMS is easy to learn.

 

[Muthuraja.M]

Thanks vardan ..

Is verilog - A can be simulated using Modelsim ?

 

[vardan]

I used ModelSim years ago, it hadn't such possibility. Check the website for the current status.

In the flows I worked with, Verilog-A will require analog simulator. Standalone Verilog-A design (without Verilog-D) can be simulated by some SPICE simulators.

 

[Muthuraja.M]

ok thank u for your reply....

how the RC network is build by verilog i.e how we can write the code for RC network ?

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using verilog ?

 

[dave_59]

Basic ModelSim does not support Verilog-A, but Questa does: www.mentor.com/products/fv/advance_ms/