wat is the lacthup problem?

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HI

Can u be elaborate ple in what sence u want to know about latch up problem?
Like in verlilog prog while the time of writting code we infer a latch and because of which we don't get the exact functionality...
 

In CMOS fabrication due to its structure there may be chance for inferring Parasitic Transistors , due to which there will a connection between vcc and vdd. Due to this IC may get damage. this is Latchup effect.

u can get more info from this..
 

Please refer the following page for more details.

**broken link removed**

I have used PTAP & NTAP( Well & Substrate Connection) cells to avoid the Latch-Up violations.
 

There is a low impedence path occured inbetween Vdd and Vss.So because of that huge amount of current flows in the device and causes to destroy the device permanently.The avoide this latchup we use guardrings.

For mor details ple reffer Kang Digital VLSI deisgn.
 

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