warning: verilog 'assign' or 'tran' statements are written out. (vo-4)

[ujas]

Due to assign statement, post synthesis file is not working with testbench.
comparator module has assign statement.
how can i avoid assign statement?
in synthesized why tool gives 4 counter module ? its supposed to be 2 counter.

`timescale 1ns / 1ps

module pwm( clk , in, s1, s2, rst, lem, dead);
input clk,rst,lem;
input [7:0] in,dead;
output reg s1,s2;

wire [7:0] m,m2,m3,ao;
wire n,o,p,ss1,o2,o3,orr,z2,ss2,p2,mx1,mx2;



always @(ss1,ss2)
begin
if (!rst)
begin
s1 <= ss1;

s2 <= ss2;
end
else
begin
s1 <= 0;

s2 <= 0;

end
end

updowncounter r1 (m,lem,clk,rst);

zerodetector r2(m,n);
comparator r3(m,in,o);
sr r4(n,o,p);
XOR r5 (ss1,p,lem);
adder r6(in,dead,ao);
updowncounter r7(m2,!lem,clk,rst);
comparator r8(m2,dead,o2);

comparator r10(m,ao,o3);


mux r13 (lem,o3,o2,mx1);
mux r14 (lem,o2,o3,mx2);
or2 r15(mx2,n,orr);
sr r16 (mx1,orr,ss2);

endmodule

module mux(s,a,b,c);
input a,b,s ;
output c;
wire sb,x,y;
not (sb,s);
and (x,sb,a);
and (y,s,b);
or (c,x,y);

endmodule

module or2(a,b,c);
input a,b;
output c;
reg c;
always @(a ,b)
c <= a | b;
endmodule

module adder(a,b,c);
input [7:0] a;
input [7:0] b;
output [7:0] c;

wire [7:0] c;

assign c=a+b;

endmodule


module XOR (z,y,x);
input y,x;
output z;
reg z;
always @(y,x)
z <= (x&(~y)) | ((~x)&y);

endmodule

module zerodetector(a,b//clk
);
//input clk;
input [7:0] a;
output b;
reg b;

always @( a)
begin

if (a == 8'b0)
b <=1;
else
b <=0;
end

endmodule


module comparator(
a,
b,
c
);

input [7:0] a,b;
output reg c;
//reg c;
//wire c;
//assign c=(a==b)?1:0;
always @ (a,b)
begin
if (a == b)
c <=1;
else
c <=0 ;
end

endmodule



module sr( s,r,q//,clk
);
//input clk;
output q;
reg q,qbar;
input s,r;
always @(s,r,qbar,q)
begin
q <= !(r | qbar);
qbar <= !(s | q);
end
endmodule

module updowncounter( z,up_down,clk2,reset
);

//----------Output Ports--------------
output [7:0] z;

//------------Input Ports--------------
input up_down,clk2, reset
;


reg [7:0] out;

always @(posedge clk2)
begin
if (reset)
out <= 8'b0 ;
else
if (!up_down)
out <= out + 1;
else

out <= out - 1;

end

assign z=out;



endmodule

synthesized netlist with TSMC 0.18um

module updowncounter_0_DW01_inc_0 ( A, SUM );
input [7:0] A;
output [7:0] SUM;

wire [7:2] carry;

ADDHX1M U1_1_6 ( .A(A[6]), .B(carry[6]), .CO(carry[7]), .S(SUM[6]) );
ADDHX1M U1_1_2 ( .A(A[2]), .B(carry[2]), .CO(carry[3]), .S(SUM[2]) );
ADDHX1M U1_1_3 ( .A(A[3]), .B(carry[3]), .CO(carry[4]), .S(SUM[3]) );
ADDHX1M U1_1_4 ( .A(A[4]), .B(carry[4]), .CO(carry[5]), .S(SUM[4]) );
ADDHX1M U1_1_5 ( .A(A[5]), .B(carry[5]), .CO(carry[6]), .S(SUM[5]) );
ADDHX1M U1_1_1 ( .A(A[1]), .B(A[0]), .CO(carry[2]), .S(SUM[1]) );
INVX2M U1 ( .A(A[0]), .Y(SUM[0]) );
XOR2X1M U2 ( .A(carry[7]), .B(A[7]), .Y(SUM[7]) );
endmodule


module updowncounter_0 ( z, up_down, clk2, reset );
output [7:0] z;
input up_down, clk2, reset;
wire N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17, N18, N19,
N20, N21, N22, N23, N24, N25, N26, N27, N28, n1, n2, n3, n4, n5, n6,
n7, n8;

updowncounter_0_DW01_inc_0 add_164 ( .A(z), .SUM({N12, N11, N10, N9, N8, N7,
N6, N5}) );
DFFQX2M \out_reg[7] ( .D(N28), .CK(clk2), .Q(z[7]) );
DFFQX2M \out_reg[3] ( .D(N24), .CK(clk2), .Q(z[3]) );
DFFQX2M \out_reg[6] ( .D(N27), .CK(clk2), .Q(z[6]) );
DFFQX2M \out_reg[4] ( .D(N25), .CK(clk2), .Q(z[4]) );
DFFQX2M \out_reg[5] ( .D(N26), .CK(clk2), .Q(z[5]) );
DFFQX2M \out_reg[2] ( .D(N23), .CK(clk2), .Q(z[2]) );
DFFQX2M \out_reg[1] ( .D(N22), .CK(clk2), .Q(z[1]) );
DFFQX2M \out_reg[0] ( .D(N21), .CK(clk2), .Q(z[0]) );
AO22X2M U3 ( .A0(N11), .A1(n1), .B0(N19), .B1(n2), .Y(N27) );
AO22X2M U4 ( .A0(N10), .A1(n1), .B0(N18), .B1(n2), .Y(N26) );
AO22X2M U5 ( .A0(N12), .A1(n1), .B0(N20), .B1(n2), .Y(N28) );
INVX2M U6 ( .A(z[0]), .Y(N13) );
AO22X2M U7 ( .A0(N9), .A1(n1), .B0(N17), .B1(n2), .Y(N25) );
AO22X2M U8 ( .A0(N8), .A1(n1), .B0(N16), .B1(n2), .Y(N24) );
AO22X2M U9 ( .A0(N7), .A1(n1), .B0(N15), .B1(n2), .Y(N23) );
AO22X2M U10 ( .A0(N6), .A1(n1), .B0(N14), .B1(n2), .Y(N22) );
AO22X2M U11 ( .A0(N5), .A1(n1), .B0(N13), .B1(n2), .Y(N21) );
NOR2X2M U12 ( .A(reset), .B(up_down), .Y(n1) );
NOR2BX2M U13 ( .AN(up_down), .B(reset), .Y(n2) );
NAND2BX1M U14 ( .AN(z[1]), .B(N13), .Y(n3) );
OAI2BB1X1M U15 ( .A0N(z[0]), .A1N(z[1]), .B0(n3), .Y(N14) );
OR2X1M U16 ( .A(n3), .B(z[2]), .Y(n4) );
OAI2BB1X1M U17 ( .A0N(n3), .A1N(z[2]), .B0(n4), .Y(N15) );
OR2X1M U18 ( .A(n4), .B(z[3]), .Y(n5) );
OAI2BB1X1M U19 ( .A0N(n4), .A1N(z[3]), .B0(n5), .Y(N16) );
OR2X1M U20 ( .A(n5), .B(z[4]), .Y(n6) );
OAI2BB1X1M U21 ( .A0N(n5), .A1N(z[4]), .B0(n6), .Y(N17) );
OR2X1M U22 ( .A(n6), .B(z[5]), .Y(n7) );
OAI2BB1X1M U23 ( .A0N(n6), .A1N(z[5]), .B0(n7), .Y(N18) );
XNOR2X1M U24 ( .A(z[6]), .B(n7), .Y(N19) );
NOR2X1M U25 ( .A(z[6]), .B(n7), .Y(n8) );
XOR2X1M U26 ( .A(z[7]), .B(n8), .Y(N20) );
endmodule


module zerodetector ( a, b );
input [7:0] a;
output b;
wire n1, n2;

AND2X2M U1 ( .A(n1), .B(n2), .Y(b) );
NOR4X1M U2 ( .A(a[7]), .B(a[6]), .C(a[5]), .D(a[4]), .Y(n2) );
NOR4X1M U3 ( .A(a[3]), .B(a[2]), .C(a[1]), .D(a[0]), .Y(n1) );
endmodule


module comparator_0 ( a, b, c );
input [7:0] a;
input [7:0] b;
output c;
wire N0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12;
assign c = N0;

XNOR2X1M U1 ( .A(b[6]), .B(a[6]), .Y(n4) );
XNOR2X1M U2 ( .A(b[5]), .B(a[5]), .Y(n3) );
XNOR2X1M U3 ( .A(b[4]), .B(a[4]), .Y(n2) );
XNOR2X1M U4 ( .A(b[3]), .B(a[3]), .Y(n1) );
NAND4X1M U5 ( .A(n4), .B(n3), .C(n2), .D(n1), .Y(n12) );
NOR2BX1M U6 ( .AN(a[0]), .B(b[0]), .Y(n5) );
OAI2B2X1M U7 ( .A1N(b[1]), .A0(n5), .B0(a[1]), .B1(n5), .Y(n8) );
NOR2BX1M U8 ( .AN(b[0]), .B(a[0]), .Y(n6) );
OAI2B2X1M U9 ( .A1N(a[1]), .A0(n6), .B0(b[1]), .B1(n6), .Y(n7) );
CLKNAND2X2M U10 ( .A(n8), .B(n7), .Y(n11) );
XOR2X1M U11 ( .A(b[7]), .B(a[7]), .Y(n10) );
XOR2X1M U12 ( .A(b[2]), .B(a[2]), .Y(n9) );
NOR4X1M U13 ( .A(n12), .B(n11), .C(n10), .D(n9), .Y(N0) );
endmodule


module sr_0 ( s, r, q );
input s, r;
output q;


AOI2BB1X8M U1 ( .A0N(s), .A1N(q), .B0(r), .Y(q) );
endmodule


module XOR ( z, y, x );
input y, x;
output z;


XOR2X2M U1 ( .A, .B(x), .Y(z) );
endmodule


module adder_DW01_add_0 ( A, B, CI, SUM, CO );
input [7:0] A;
input [7:0] B;
output [7:0] SUM;
input CI;
output CO;
wire n1;
wire [7:1] carry;

XOR3XLM U1_7 ( .A(A[7]), .B(B[7]), .C(carry[7]), .Y(SUM[7]) );
ADDFX2M U1_1 ( .A(A[1]), .B(B[1]), .CI(n1), .CO(carry[2]), .S(SUM[1]) );
ADDFX2M U1_2 ( .A(A[2]), .B(B[2]), .CI(carry[2]), .CO(carry[3]), .S(SUM[2])
);
ADDFX2M U1_6 ( .A(A[6]), .B(B[6]), .CI(carry[6]), .CO(carry[7]), .S(SUM[6])
);
ADDFX2M U1_3 ( .A(A[3]), .B(B[3]), .CI(carry[3]), .CO(carry[4]), .S(SUM[3])
);
ADDFX2M U1_5 ( .A(A[5]), .B(B[5]), .CI(carry[5]), .CO(carry[6]), .S(SUM[5])
);
ADDFX2M U1_4 ( .A(A[4]), .B(B[4]), .CI(carry[4]), .CO(carry[5]), .S(SUM[4])
);
AND2X2M U1 ( .A(B[0]), .B(A[0]), .Y(n1) );
XOR2X2M U2 ( .A(B[0]), .B(A[0]), .Y(SUM[0]) );
endmodule


module adder ( a, b, c );
input [7:0] a;
input [7:0] b;
output [7:0] c;


adder_DW01_add_0 add_76 ( .A(a), .B(b), .CI(1'b0), .SUM(c) );
endmodule


module updowncounter_1_DW01_inc_0 ( A, SUM );
input [7:0] A;
output [7:0] SUM;

wire [7:2] carry;

ADDHX1M U1_1_6 ( .A(A[6]), .B(carry[6]), .CO(carry[7]), .S(SUM[6]) );
ADDHX1M U1_1_5 ( .A(A[5]), .B(carry[5]), .CO(carry[6]), .S(SUM[5]) );
ADDHX1M U1_1_4 ( .A(A[4]), .B(carry[4]), .CO(carry[5]), .S(SUM[4]) );
ADDHX1M U1_1_3 ( .A(A[3]), .B(carry[3]), .CO(carry[4]), .S(SUM[3]) );
ADDHX1M U1_1_2 ( .A(A[2]), .B(carry[2]), .CO(carry[3]), .S(SUM[2]) );
ADDHX1M U1_1_1 ( .A(A[1]), .B(A[0]), .CO(carry[2]), .S(SUM[1]) );
INVX2M U1 ( .A(A[0]), .Y(SUM[0]) );
XOR2X1M U2 ( .A(carry[7]), .B(A[7]), .Y(SUM[7]) );
endmodule


module updowncounter_1 ( z, up_down, clk2, reset );
output [7:0] z;
input up_down, clk2, reset;
wire N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17, N18, N19,
N20, N21, N22, N23, N24, N25, N26, N27, N28, n3, n4, n5, n6, n7, n8,
n9, n10;

updowncounter_1_DW01_inc_0 add_164 ( .A(z), .SUM({N12, N11, N10, N9, N8, N7,
N6, N5}) );
DFFQX2M \out_reg[7] ( .D(N28), .CK(clk2), .Q(z[7]) );
DFFQX2M \out_reg[3] ( .D(N24), .CK(clk2), .Q(z[3]) );
DFFQX2M \out_reg[4] ( .D(N25), .CK(clk2), .Q(z[4]) );
DFFQX2M \out_reg[5] ( .D(N26), .CK(clk2), .Q(z[5]) );
DFFQX2M \out_reg[6] ( .D(N27), .CK(clk2), .Q(z[6]) );
DFFQX2M \out_reg[2] ( .D(N23), .CK(clk2), .Q(z[2]) );
DFFQX2M \out_reg[1] ( .D(N22), .CK(clk2), .Q(z[1]) );
DFFQX2M \out_reg[0] ( .D(N21), .CK(clk2), .Q(z[0]) );
AO22X2M U3 ( .A0(N11), .A1(n10), .B0(N19), .B1(n9), .Y(N27) );
AO22X2M U4 ( .A0(N10), .A1(n10), .B0(N18), .B1(n9), .Y(N26) );
AO22X2M U5 ( .A0(N12), .A1(n10), .B0(N20), .B1(n9), .Y(N28) );
INVX2M U6 ( .A(z[0]), .Y(N13) );
AO22X2M U7 ( .A0(N9), .A1(n10), .B0(N17), .B1(n9), .Y(N25) );
AO22X2M U8 ( .A0(N8), .A1(n10), .B0(N16), .B1(n9), .Y(N24) );
AO22X2M U9 ( .A0(N7), .A1(n10), .B0(N15), .B1(n9), .Y(N23) );
AO22X2M U10 ( .A0(N6), .A1(n10), .B0(N14), .B1(n9), .Y(N22) );
AO22X2M U11 ( .A0(N5), .A1(n10), .B0(N13), .B1(n9), .Y(N21) );
NOR2X2M U12 ( .A(reset), .B(up_down), .Y(n10) );
NOR2BX2M U13 ( .AN(up_down), .B(reset), .Y(n9) );
NAND2BX1M U14 ( .AN(z[1]), .B(N13), .Y(n3) );
OAI2BB1X1M U15 ( .A0N(z[0]), .A1N(z[1]), .B0(n3), .Y(N14) );
OR2X1M U16 ( .A(n3), .B(z[2]), .Y(n4) );
OAI2BB1X1M U17 ( .A0N(n3), .A1N(z[2]), .B0(n4), .Y(N15) );
OR2X1M U18 ( .A(n4), .B(z[3]), .Y(n5) );
OAI2BB1X1M U19 ( .A0N(n4), .A1N(z[3]), .B0(n5), .Y(N16) );
OR2X1M U20 ( .A(n5), .B(z[4]), .Y(n6) );
OAI2BB1X1M U21 ( .A0N(n5), .A1N(z[4]), .B0(n6), .Y(N17) );
OR2X1M U22 ( .A(n6), .B(z[5]), .Y(n7) );
OAI2BB1X1M U23 ( .A0N(n6), .A1N(z[5]), .B0(n7), .Y(N18) );
XNOR2X1M U24 ( .A(z[6]), .B(n7), .Y(N19) );
NOR2X1M U25 ( .A(z[6]), .B(n7), .Y(n8) );
XOR2X1M U26 ( .A(z[7]), .B(n8), .Y(N20) );
endmodule


module comparator_2 ( a, b, c );
input [7:0] a;
input [7:0] b;
output c;
wire N0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12;
assign c = N0;

XNOR2X1M U1 ( .A(b[6]), .B(a[6]), .Y(n4) );
XNOR2X1M U2 ( .A(b[5]), .B(a[5]), .Y(n3) );
XNOR2X1M U3 ( .A(b[4]), .B(a[4]), .Y(n2) );
XNOR2X1M U4 ( .A(b[3]), .B(a[3]), .Y(n1) );
NAND4X1M U5 ( .A(n4), .B(n3), .C(n2), .D(n1), .Y(n12) );
NOR2BX1M U6 ( .AN(a[0]), .B(b[0]), .Y(n5) );
OAI2B2X1M U7 ( .A1N(b[1]), .A0(n5), .B0(a[1]), .B1(n5), .Y(n8) );
NOR2BX1M U8 ( .AN(b[0]), .B(a[0]), .Y(n6) );
OAI2B2X1M U9 ( .A1N(a[1]), .A0(n6), .B0(b[1]), .B1(n6), .Y(n7) );
CLKNAND2X2M U10 ( .A(n8), .B(n7), .Y(n11) );
XOR2X1M U11 ( .A(b[7]), .B(a[7]), .Y(n10) );
XOR2X1M U12 ( .A(b[2]), .B(a[2]), .Y(n9) );
NOR4X1M U13 ( .A(n12), .B(n11), .C(n10), .D(n9), .Y(N0) );
endmodule


module comparator_1 ( a, b, c );
input [7:0] a;
input [7:0] b;
output c;
wire N0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12;
assign c = N0;

XNOR2X1M U1 ( .A(b[6]), .B(a[6]), .Y(n4) );
XNOR2X1M U2 ( .A(b[5]), .B(a[5]), .Y(n3) );
XNOR2X1M U3 ( .A(b[4]), .B(a[4]), .Y(n2) );
XNOR2X1M U4 ( .A(b[3]), .B(a[3]), .Y(n1) );
NAND4X1M U5 ( .A(n4), .B(n3), .C(n2), .D(n1), .Y(n12) );
NOR2BX1M U6 ( .AN(a[0]), .B(b[0]), .Y(n5) );
OAI2B2X1M U7 ( .A1N(b[1]), .A0(n5), .B0(a[1]), .B1(n5), .Y(n8) );
NOR2BX1M U8 ( .AN(b[0]), .B(a[0]), .Y(n6) );
OAI2B2X1M U9 ( .A1N(a[1]), .A0(n6), .B0(b[1]), .B1(n6), .Y(n7) );
CLKNAND2X2M U10 ( .A(n8), .B(n7), .Y(n11) );
XOR2X1M U11 ( .A(b[7]), .B(a[7]), .Y(n10) );
XOR2X1M U12 ( .A(b[2]), .B(a[2]), .Y(n9) );
NOR4X1M U13 ( .A(n12), .B(n11), .C(n10), .D(n9), .Y(N0) );
endmodule


module mux_0 ( s, a, b, c );
input s, a, b;
output c;


AO2B2X2M U1 ( .B0(s), .B1(b), .A0(a), .A1N(s), .Y(c) );
endmodule


module mux_1 ( s, a, b, c );
input s, a, b;
output c;


AO2B2X2M U1 ( .B0(s), .B1(b), .A0(a), .A1N(s), .Y(c) );
endmodule


module or2 ( a, b, c );
input a, b;
output c;


OR2X2M U1 ( .A(a), .B(b), .Y(c) );
endmodule


module sr_1 ( s, r, q );
input s, r;
output q;


AOI2BB1X8M U1 ( .A0N(s), .A1N(q), .B0(r), .Y(q) );
endmodule


module pwm ( clk, in, s1, s2, rst, lem, dead );
input [7:0] in;
input [7:0] dead;
input clk, rst, lem;
output s1, s2;
wire ss1, ss2, n, o, p, o2, o3, mx1, mx2, orr, n2;
wire [7:0] m;
wire [7:0] ao;
wire [7:0] m2;

updowncounter_0 r1 ( .z(m), .up_down(lem), .clk2(clk), .reset(rst) );
zerodetector r2 ( .a(m), .b );
comparator_0 r3 ( .a(m), .b(in), .c(o) );
sr_0 r4 ( .s, .r(o), .q(p) );
XOR r5 ( .z(ss1), .y(p), .x(lem) );
adder r6 ( .a(in), .b(dead), .c(ao) );
updowncounter_1 r7 ( .z(m2), .up_down(n2), .clk2(clk), .reset(rst) );
comparator_2 r8 ( .a(m2), .b(dead), .c(o2) );
comparator_1 r10 ( .a(m), .b(ao), .c(o3) );
mux_0 r13 ( .s(lem), .a(o3), .b(o2), .c(mx1) );
mux_1 r14 ( .s(lem), .a(o2), .b(o3), .c(mx2) );
or2 r15 ( .a(mx2), .b, .c(orr) );
sr_1 r16 ( .s(mx1), .r(orr), .q(ss2) );
INVX2M U5 ( .A(lem), .Y(n2) );
NOR2BX2M U6 ( .AN(ss1), .B(rst), .Y(s1) );
NOR2BX2M U7 ( .AN(ss2), .B(rst), .Y(s2) );
endmodule

 

[dpaul]

sorry your question isn't clear to me.
What is the problem is using assign statements for a comparator design (it can be done since this comparator of yours doesn't need to be sequential)?

module comparator(
a,
b,
c
);

input [7:0] a,b;
output reg c;
//reg c;
//wire c;
//assign c=(a==b)?1:0;
always @ (a,b)
begin
if (a == b)
c <=1;
else
c <=0 ;
end

endmodule

I also see that you had used "wire c;" and not "output wire c;"

 

[ujas]

sorry your question isn't clear to me.
What is the problem is using assign statements for a comparator design (it can be done since this comparator of yours doesn't need to be sequential)?

module comparator(
a,
b,
c
);

input [7:0] a,b;
output reg c;
//reg c;
//wire c;
//assign c=(a==b)?1:0;
always @ (a,b)
begin
if (a == b)
c <=1;
else
c <=0 ;
end

endmodule

I also see that you had used "wire c;" and not "output wire c;"

I mean after i synthesize all modules , In synthesized netlist, comparator comes with assign statement.
Please check synthesized netlist.
Did you see?

Thanks man for reply.

 

[sharath666]

That depends on how the synthesis tool infers the RTL. This is pure combinational logic and it is possible for the tool to infer an assign statement...

 

[dpaul]

I wouldn't care much about what's there in the netlists as long as my netlist-simulation results are comparable and acceptable to RTL-simulation results. Have you tried a netlist-simulation? If not do it, and compare the results yourself.

 

[ads-ee]

I wouldn't care much about what's there in the netlists as long as my netlist-simulation results are comparable and acceptable to RTL-simulation results. Have you tried a netlist-simulation? If not do it, and compare the results yourself.

Now that we've come full circle...

Due to assign statement, post synthesis file is not working with testbench.

Maybe you should explain exactly what you mean by the above statement, emphasized by the bold font.

How is it not working due to the assign? You never gave the simulation error that you are seeing. Having the netlist and the testbench does very little good unless a forum member has the exact library you are using. Needless to say you never even told anyone what tool chain you are using that has a problem with the assign statement in the netlist.

 

[ujas]

Now that we've come full circle...



Maybe you should explain exactly what you mean by the above statement, emphasized by the bold font.

How is it not working due to the assign? You never gave the simulation error that you are seeing. Having the netlist and the testbench does very little good unless a forum member has the exact library you are using. Needless to say you never even told anyone what tool chain you are using that has a problem with the assign statement in the netlist.

Hi Its my bad. Here is the error I'm getting in Modelsim when simulating gate level netlist.
18m.v is header file which has all basic cells.
Please tell me what you think about this error:

** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r1/\out_reg[0]
# ** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r1/\out_reg[1]
# ** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r1/\out_reg[2]
# ** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r1/\out_reg[3]
# ** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r1/\out_reg[4]
# ** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r1/\out_reg[7]
# ** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r1/\out_reg[5]
# ** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r1/\out_reg[6]
# ** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r7/\out_reg[0]
# ** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r7/\out_reg[1]
# ** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r7/\out_reg[2]
# ** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r7/\out_reg[3]
# ** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r7/\out_reg[4]
# ** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r7/\out_reg[7]
# ** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r7/\out_reg[5]
# ** Error: 18m.v(8384): $hold( negedge CKN &&& (flag == 1):112 ns, posedge D:112 ns, 500 ps );
# Time: 112 ns Iteration: 2 Instance: /dut/uut/r7/\out_reg[6]
# ** Error: 18m.v(8385): $hold( negedge CKN &&& (flag == 1):116 ns, negedge D:116 ns, 500 ps );
# Time: 116 ns Iteration: 1 Instance: /dut/uut/r1/\out_reg[1]
# ** Error: 18m.v(8385): $hold( negedge CKN &&& (flag == 1):116 ns, negedge D:116 ns, 500 ps );
# Time: 116 ns Iteration: 1 Instance: /dut/uut/r1/\out_reg[2]
# ** Error: 18m.v(8385): $hold( negedge CKN &&& (flag == 1):116 ns, negedge D:116 ns, 500 ps );
# Time: 116 ns Iteration: 1 Instance: /dut/uut/r1/\out_reg[3]
# ** Error: 18m.v(8385): $hold( negedge CKN &&& (flag == 1):116 ns, negedge D:116 ns, 500 ps );
# Time: 116 ns Iteration: 1 Instance: /dut/uut/r1/\out_reg[4]
# ** Error: 18m.v(8385): $hold( negedge CKN &&& (flag == 1):116 ns, negedge D:116 ns, 500 ps );
# Time: 116 ns Iteration: 1 Instance: /dut/uut/r1/\out_reg[5]

 

[sharath666]

These messages indicate hold violations on the instances indicated..They have nothing to do with assign statements in your netlist..

 

[ujas]

These messages indicate hold violations on the instances indicated..They have nothing to do with assign statements in your netlist..

Yes man. You'r right.
So is there way i can fix it ?
18m.v is TSMC header file provided by university.

 

[dpaul]

see here - http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html

I wouldn't mess with the idea of playing with the library cell widths. Generally the back-end engineers fix HOLD violations.

As a front-end guy, play around with your CLK freq (if that is allowed) to see if you can get it done.