Dec 15, 2016 #1 T taaha651 Newbie level 2 Joined Dec 2, 2016 Messages 2 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 25 Hi, i am interfacing virtex 5 with ddr2. I have generated a code for ddr2 using MIG. i am getting the following warning. WARNING:Timing:3223 - Timing constraint TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FROM TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO TIMEGRP "RAMS" TS_SYS_clk0 * 4; ignored during timing analysis. i dont know if this warning is serious. can somebody explain what this means?
Hi, i am interfacing virtex 5 with ddr2. I have generated a code for ddr2 using MIG. i am getting the following warning. WARNING:Timing:3223 - Timing constraint TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FROM TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO TIMEGRP "RAMS" TS_SYS_clk0 * 4; ignored during timing analysis. i dont know if this warning is serious. can somebody explain what this means?