Warning in Xilinx ISE during synthesis / VHDL

[graphene]

Hallo,

I am using Xilinx ISE to program my FPGA using VHDL.

When I compile and synthesise a code despite ensuring its syntax and logic correctness, the synthesiser comes out with a warning which tells "WARNING:Xst:647 - Input <clk> is never used." and so on for all inputs involved.
I am very sure that the input signals are used in the sensitivity list of my process and its statements. Also ignoring the warning when I see the RTL schematic or the technology schematic, I just find the block with inpputs,outputs floated. I cleaned up my project files, again no use.

I am including my code below. Perhaps, the same warning came eve for the simplest D-flipflop a couple of days ago but now now.

I googled and read several forums but I am unable to understand it.



My question is not about how to deal with a warning but rather an error that is shown as a warning.


Please let me know your suggestions and recommendations.

LG

library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE. STD_LOGIC_ARITH.all;
----

entity mit_nasa is
	port(
	clk			: in std_logic;
	fsm_in		: in std_logic;
	rst			: in std_logic;
	fsm_out		: out std_logic_vector (1 downto 0)
	);
end mit_nasa;

architecture arc_mit_nasa of mit_nasa is

	type state_type is (ST0,ST1);
	signal present_state, next_state: state_type;
	
begin
		rst_proc: process (clk, rst, next_state) 
		begin
			if (rst='1') then
			present_state	<= ST0;
			elsif (rising_edge(clk)) then
			present_state <= next_state;
			end if;
		end process rst_proc; 
	
		comb_process: process (present_state, fsm_in)
		begin
		fsm_out<="00";
		case present_state is 
			when ST0=>
				fsm_out<="00";
				if fsm_in<='1' then next_state<=ST1;
				else next_state<=ST0;
				end if;
			when ST1 =>
				fsm_out<="00";
				if fsm_in<='1' then next_state<=ST0;
				else next_state<=ST1;
				end if;
			when others =>
				fsm_out<="00";
				next_state<=ST0;
		end case;
		end process comb_process;

end arc_mit_nasa;

 

[TrickyDicky]

The error is because fsm_out is locked at "00", and so all of your logic is removed. Hence the clock input isnt used.

Logic is removed when the synthesisor determins that it has no effect on an output. In this case, as the only output, FSM_out is always "00", it does not need any logic to do that.

 

[graphene]

Thank you mate. I also tried without that particular statement.

Even now again I synthesised, despite the same warning and same floating schematic. Still unresolved. Any suggestions ??


and also any reason for ISE being behind the warning or is it the code .

 

[TrickyDicky]

Its the code. Like I said, any logic that has no effect on an output will be removed. So removing the assignment to fsm_out is just as bad as leaving it "00" in all states. If you make it a different value in each state, you wont get the warning.

ISE is behind the warning because it generates the logic that goes in the Chip, but it's your code thats behind the warning. Its not an error because you may legitimately have pins that are not connected eg. because you have an interface that is only connected with specific parameters

 

[graphene]

Hi TrickyDicky... I sincerely appreciate your time..
.
However, what I am still not getting is that in my code even if I consider only the first process (involving clk and rst inputs) and ignore the second process or vice versa it is still the same. which atleast demands the fact that one among the 3 inputs shall atleast be pinned but all are floated.

2) As I mentioned before if happened with the simplest D-flipflop and now I am trying a series of codes from tutorial and some works some doesnt.

I am now in the berge of simply excuting codes from internet and despite that critical warning in few of those attempts...

 

[TrickyDicky]

Forget about the code - think about the logic.
Your code generates logic that does not connect to an output. Therefore it is redundant and removed - hence the clk unused warning.