sanketphapale45
Newbie level 1
Hello,
I have a standard file consisting of more thane one standard modules. but i wanted to use only 1 module from that file.
suppose
I want to use module_2 and not others. When I source module_list() in vcs command i got lot many errors of unused modules. Is there any method to source only particular module/part of verilog file instead of sourcing complete file. I can't edit .sv file. I have only vcs command (make file) in my hand...
Please respond..
Thnks
,Sanket
I have a standard file consisting of more thane one standard modules. but i wanted to use only 1 module from that file.
suppose
Code:
module module_list();
module_1....
module_2....
.
.
.
module_n...
end modulePlease respond..
Thnks
,Sanket