Hello all,
Please I am trying to design a walsh code of length 8 on FPGA using VHDL codes. I am using 2 T-flip flops, 3 AND gates and 1 OR gate to implement this design. I have been unsuccessful and really need some help as I am new to using VHDL code language. What I have so far shown below synthesizes but the simulation report does not reproduce the accurate result. Any help will be greatly appreciated. Thanks.
Library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY walsh8 IS
PORT(clk: IN STD_LOGIC;
RESET: IN STD_LOGIC;
u0: IN STD_LOGIC;
u1: IN STD_LOGIC;
u2: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC);
END walsh8;
ARCHITECTURE fpga OF walsh8 IS
SIGNAL Q1: STD_LOGIC;
SIGNAL Q2: STD_LOGIC;
SIGNAL T : STD_LOGIC := '0';
BEGIN
PROCESS(clk, RESET)
BEGIN
IF (reset = '1') THEN
T <= '0';
ELSIF (clk='1' AND clk'EVENT) THEN
T <= NOT T;
END IF;
END PROCESS;
PROCESS (clk, RESET)
BEGIN
IF (RESET = '1') THEN
Q1 <= '0';
Q2 <= '0';
ELSIF(clk='1' AND clk'EVENT) THEN
Q1 <= T XOR Q1;
Q2 <= Q1 XOR Q2;
END IF;
OUTPUT <= ((u0 AND T) OR (u1 AND Q1) OR (u2 AND Q2));
END PROCESS;
END fpga;
PROCESS(clk,RESET,T)
BEGIN
IF (reset = '1') THEN
T <= "00000000";
ELSIF (clk='1' AND clk'EVENT) THEN
T <= "01010101";
END IF;
END PROCESS;
its not ideal -- the process will get re-evaluated each time T changes, but a change in T will not trigger either the "if reset" or the "else if rising_edge clk" portions. There is no need to re-evaluated the process whenever T changes. Still, it doesn't actually affect synthesis, as synthesis will ignore the sensitivity list even if such wouldn't agree with sim. And it doesn't change the sim results, as the re-evaluation doesn't update any signals -- it just wastes time.I think this is wrong , you use T in your sensitivity list when you are actually modifying T inside the process, there in no need for T to be there.
URGENT!!! FOR PROJECT!
Hello everyone,
I posted a problem I am currently having with my project using VHDL on FPGA. I am using Altera DE2-70 board with Quartus II 9.1 web edition. I have worked more on the problem and now it synthesizes and simulates however I am not getting the expected result. I get a few warnings after analysis and synthesis. Please review my program below and make suggestions please. Its urgent since it is my project that is due in another 48 hours. Thanks for your input.
Library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY walsh8 IS
PORT(clk: IN STD_LOGIC;
RESET: IN STD_LOGIC;
u0: IN STD_LOGIC;
u1: IN STD_LOGIC;
u2: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END walsh8;
ARCHITECTURE fpga OF walsh8 IS
SIGNAL Q1: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL Q2: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL T : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL X : STD_LOGIC_VECTOR (7 DOWNTO 0):=(OTHERS => '0');
SIGNAL Y : STD_LOGIC_VECTOR (7 DOWNTO 0):=(OTHERS => '0');
SIGNAL Z : STD_LOGIC_VECTOR (7 DOWNTO 0):=(OTHERS => '0');
BEGIN
PROCESS(clk,RESET,T)
BEGIN
IF (reset = '1') THEN
T <= "00000000";
ELSIF (clk='1' AND clk'EVENT) THEN
T <= "01010101";
END IF;
END PROCESS;
PROCESS (clk,RESET,Q1,Q2)
BEGIN
IF (RESET = '1') THEN
Q1 <= "00000000";
Q2 <= "00000000";
ELSIF(clk='1' AND clk'EVENT) THEN
Q1 <= T XOR Q1;
Q2 <= Q1 XOR Q2;
END IF;
END PROCESS;
PROCESS (clk,RESET,u0,u1,u2,X,Y,Z)
BEGIN
IF (RESET = '1') THEN
IF (clk = '1' AND clk 'EVENT) THEN
IF u0 <= '0' THEN
X <= "00000000";
ELSIF u0 <= '1' THEN
X <= "11111111";
END IF;
IF u1 <= '0' THEN
Y <= "00000000";
ELSIF u1 <= '1' THEN
Y <= "11111111";
END IF;
IF u2 <= '0' THEN
Z <= "00000000";
ELSIF u2 <= '1' THEN
Z <= "11111111";
END IF;
END IF;
END IF;
END PROCESS;
OUTPUT <= ((X AND T) OR (Y AND Q1) OR (Z AND Q2));
END fpga;
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off walsh8 -c walsh8
Info: Found 2 design units, including 1 entities, in source file walsh8.vhd
Info: Elaborating entity "walsh8" for the top level hierarchy
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "OUTPUT[1]" is stuck at GND
Warning (13410): Pin "OUTPUT[3]" is stuck at GND
Warning (13410): Pin "OUTPUT[5]" is stuck at GND
Warning (13410): Pin "OUTPUT[7]" is stuck at GND
Info: 12 registers lost all their fanouts during netlist optimizations. The first 12 are displayed below.
Info: Register "X[1]" lost all its fanouts during netlist optimizations.
Info: Register "X[3]" lost all its fanouts during netlist optimizations.
Info: Register "X[5]" lost all its fanouts during netlist optimizations.
Info: Register "X[7]" lost all its fanouts during netlist optimizations.
Info: Register "Y[1]" lost all its fanouts during netlist optimizations.
Info: Register "Y[3]" lost all its fanouts during netlist optimizations.
Info: Register "Y[5]" lost all its fanouts during netlist optimizations.
Info: Register "Y[7]" lost all its fanouts during netlist optimizations.
Info: Register "Z[1]" lost all its fanouts during netlist optimizations.
Info: Register "Z[3]" lost all its fanouts during netlist optimizations.
Info: Register "Z[5]" lost all its fanouts during netlist optimizations.
Info: Register "Z[7]" lost all its fanouts during netlist optimizations.
Info: Implemented 21 device resources after synthesis - the final resource count might be different
Info: Implemented 5 input pins
Info: Implemented 8 output pins
Info: Implemented 8 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 219 megabytes
Info: Processing ended: Sun Dec 05 14:50:36 2010
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:03
I want the VHDL code to give results of a walsh code of length 8. In otherwords u0, u1, and u2 are user controlled such that if the code is correct then when u2u1u0 in that order are as follows I should get the following result:
walsh code 1: u2 = 0 u1 = 0 u0 = 0 then my result should be 00000000
walsh code 2: u2 = 0 u1 = 0 u0 =1 then 01010101
walsh code 3: u2 = 0 u1 = 1 u0 = 0 then 00110011
walsh code 4: 0 1 1 then 01100110
walsh code 5: 1 0 0 then 00001111
walsh code 6: 1 0 1 then 01011010
walsh code 7: 1 1 0 then 00111100
walsh code 8: 1 1 1 then 01101001
This is what am trying to do. Thanks so far for the input. I will to implement the suggestions made. Thanks alot.
Library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY walsh8 IS
PORT(clk: IN STD_LOGIC;
RESET: IN STD_LOGIC;
u :IN STD_LOGIC_vector(2 downto 0);
OUTPUT: OUT STD_LOGIC_vector(7 downto 0));
END walsh8;
ARCHITECTURE fpga OF walsh8 IS
BEGIN
PROCESS(clk, RESET)
BEGIN
IF (reset = '1') THEN
OUTPUT<= (others=>'0');
ELSIF (clk='1' AND clk'EVENT) THEN
case u is
when "000" => OUTPUT <="00000000";
when "001" => OUTPUT <="01010101";
when "010" => OUTPUT <="00110011";
when "011" => OUTPUT <="01100110";
when "100" => OUTPUT <="00001111";
when "101" => OUTPUT <="01011010";
when "110" => OUTPUT <="00111100";
when "111" => OUTPUT <="01101001";
when others => null;
end case;
END IF;
END PROCESS;
END fpga;
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