wait for with real type

[imbichie]

Hi All,

Can we use the real expression after WAIT FOR in VHDL.

For example,

...
signal delay : real;
...
delay <= 2.5;
...

process
begin
clk <= '1';
WAIT FOR delay;
clk <= '0';
WAIT FOR delay;
end process;

But when i am compiling the above expression i am getting error with Cadence NcSim saying that expecting an expression of type TIME.

When i googled i got one ebook from google book Digital System Design With Vhdl, here they are using the real type after the WAIT FOR.
ref : https://books.google.co.in/books?id...=y#v=onepage&q=ram memory in vhdl ams&f=false


Please anyone clarify this ?

 

[TrickyDicky]

why not make delay of type time? it takes real arguments? With your example, it doesnt know whether you mean ps, ns, us, ms, s, m or h. So either make delay of type time:

delay <= 2.5 ns;

or put the unit after the delay:

wait for delay ns;

 

[imbichie]

Hi TrickyDicky,

Here the thing is that i have a VCO module which is in VHDL AMS, so here the delay generation is from the VIN (Voltage input to the VCO) which is a real type. So when we are generating the delay from the VIN that became real. But when i am using the WAIT FOR statement i need the delay in type TIME. For real to time we can solve by multiplying with 1ns to the delay element.
Like this

process
begin
clk <= '0';
wait for delay * 1 ns;
clk <= '1';
wait for delay * 1 ns;
end process;
but the thing is that here the VCO is instantiate inside a Verilog AMS module (TOP Module), here the timescale is taken as 1ns/100ps.

Here i am confuse with the use of multiplication factor whether it is 1ns, 1ps, etc,.

Here which one i chose the multiplication factor for delay

 

[K-J]

Hi TrickyDicky,

Here the thing is that i have a VCO module which is in VHDL AMS, so here the delay generation is from the VIN (Voltage input to the VCO) which is a real type. So when we are generating the delay from the VIN that became real. But when i am using the WAIT FOR statement i need the delay in type TIME. For real to time we can solve by multiplying with 1ns to the delay element.
Like this

process
begin
clk <= '0';
wait for delay * 1 ns;
clk <= '1';
wait for delay * 1 ns;
end process;
but the thing is that here the VCO is instantiate inside a Verilog AMS module (TOP Module), here the timescale is taken as 1ns/100ps.

Here i am confuse with the use of multiplication factor whether it is 1ns, 1ps, etc,.

Here which one i chose the multiplication factor for delay

Well, your original post said set 'delay <= 2.5'...nobody in this group will be able to tell you the units of measure for the 2.5...for all we know it could be days. You need to answer that question. Once you do, you'll have the units that you need to multiply by.

As was originally suggested, the signal 'delay' should be declared as type 'time', not 'real'. Clearly it is a time, not a real. Your confusion over the units in your own posting is partly why VHDL provides 'time' as a native data type.

Kevin Jennings