Jan 4, 2018 #1 A analogTechie Junior Member level 1 Joined Nov 2, 2004 Messages 15 Helped 3 Reputation 6 Reaction score 0 Trophy points 1,281 Location USA Activity points 170 Greetings and a Happy 2018 New Year !! Could anyone please shed some light on the "VTA adder" methodology for simulating the process variation dependence of analog CMOS circuits ? Also, are there any good references on this topic ? Thanks !
Greetings and a Happy 2018 New Year !! Could anyone please shed some light on the "VTA adder" methodology for simulating the process variation dependence of analog CMOS circuits ? Also, are there any good references on this topic ? Thanks !