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VSYNC, HSYNC & Sound recovery from DVI

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shaiko

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An HDMI link consists of:

1. Red
2. Green
3. Blue
4. Pixel clock.

How are VSYNC, HSYNC & Audio encoded into the stream?
 

KlausST

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    shaiko

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srizbf

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In a DVI connection video can be successfully retrieved .
but no audio is in DVI . only thro separate channels audio can be retrieved.
for SYNC , DVI provides them.
 

shaiko

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I meant HDMI...
did you try to find your answers in wikipedia?
Or google?
Yes I have.
This is from Wikipedia:
Transition Minimized Differential Signaling (TMDS) on HDMI interleaves video, audio and auxiliary data using three different packet types, called the Video Data Period, the Data Island Period and the Control Period. During the Video Data Period, the pixels of an active video line are transmitted. During the Data Island period (which occurs during the horizontal and vertical blanking intervals), audio and auxiliary data are transmitted within a series of packets.The Control Period occurs between Video and Data Island periods.
So, I guessed information regarding HSYNC & VSYNC is embedded inside the data stream of the DATA1, DATA2, DATA3 lines.
But when exactly?
And in which of the lines DATA1/2/3?
Can you please point me to the exact place in the spec that mentions how and where the synchronization signals are embedded in the data stream?
 

KlausST

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Hi,

I´d use a dedicated HDMI receiver chip like ADV7619.

Otherwise I have to read the complete interface specifications and tell it to you, but I prefer you read it. ;-)


Klaus
 

shaiko

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I´d use a dedicated HDMI receiver chip like ADV7619.
I see where you're going - but this is an educational question.

BTW,
Because there're no dedicated control lines and the source can transmit data in one of many supported resolutions - the "Video Data Period" (as described by Wikipedia) must change according to the resolution - so how does the receiver even know when to look for the VSYNC and HSYNC ?
Sounds like the arbitration process is far from trivial...
 

FvM

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I guessed information regarding HSYNC & VSYNC is embedded inside the data stream of the DATA1, DATA2, DATA3 lines.
But when exactly?
Guessing is the opposite of reading in this case, the question is clearly answered in the DVI spec.
 

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