#1 cause of spikes is stray inductance against a hard
switched current.
Whether this is in the driver-gate-source-SW loop or
the VB-gate-SW loop, is one thing to figure out - is
the spike driven out the HO because it must follow VB
or is it that HO, gate are fine w.r.t. SW at the driver,
but the gate in-the-moment is jacked by inductive
overshoot on the upper FET source leg inductance?
Adding 'scope probes can corrupt the measurement
in high dV/dt activity, adding to the "pull" against the
common mode dV/dt and injecting currents where
there were none (or less). This could itself be a
diagnostic (if you blew up FETs more, or less, when
poking a particular flying node).
Speaking of flying nodes, I don't think 2.2uF is very
good for driving a (say) 2nF Cgg FET, and especially
not if this fly-cap has poor ESL / ESR. I would at least
give it the same HF 100nF cap as you see on the
input supplies. Maybe even more as it's a harsh dV/dt,
dI/dt environment.
the spikes are likely a result of your probing - can you post a pic please? if you have too much dead time you may be hard switching the top fets - and yes a 470nF MLCC across the 2u2 is a good idea ...
the spikes are likely a result of your probing - can you post a pic please? if you have too much dead time you may be hard switching the top fets - and yes a 470nF MLCC across the 2u2 is a good idea ...
One more thing I would like to bring to your attention is the boot strap arrangement for the upper MOSFETs. I avoided the boot-strap diode by connecting VB to + of 15V isolated DC-DC and -ve end to switching node. I have used no bootstrap diode in between them. Do you think this could cause potential problem? Additionally I used a 10k resistance between gate node and switch node to make sure gate voltage is not floating? Is that a good practice?
One more thing I would like to bring to your attention is the boot strap arrangement for the upper MOSFETs. I avoided the boot-strap diode by connecting VB to + of 15V isolated DC-DC and -ve end to switching node. I have used no bootstrap diode in between them. Do you think this could cause potential problem? Additionally I used a 10k resistance between gate node and switch node to make sure gate voltage is not floating? Is that a good practice?
here is how I connected to take the measurement of V_GS of Upper and lower MOSFET of the H-Bridge.
View attachment 156138
you should put a common mode choke ( size commensurate with current flowing ) right at the upper gate drive on the isolated DC as it comes in - this will stop all the connected stuff flapping up and down at high volts at switching frequency .... one on each high side device
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?