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Voltage ripple calculation closed loop

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pikulin03

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It seems that my question is very simple, but nevertheless I am not able to find any answer in textbooks and internet.

How is it possible to calculate the output voltage ripples in switching power converter, when there is a feedback loop closed.

For example- simple buck converter. The equation for calculation of output voltage ripples without any feedback is the following:

Vcpp=(1-D)*Vin*D/(8LC*fsw^2).

What changes if the feedback loop is added and what is the effect on these SWITCHING FREQUENCY ripples?

THANKS!
 

The bandwidth of the feedback loop must be considerably below switching frequency, thus it doesn't affect the ripple (presuming stable feedback operation).
 
THANKS!
But anyway if there is for example -30db gain margin at fsw- will this make output voltage ripples bigger ar smaller and for what ammount? Is it possible to calculate this?
The same holds for example for the noise in the system- for.ex. at fsw/2 there is -10db gain margin - how would this noise propagate to the output voltage?\ will it be attenuated or not?
 

As said, magnitude of switching frequency components isn't manipulated by the modulator.

Frequencies up to fs/2 can be manipulated. To analyse the propagation of "noise", you should know it's origin.
 
Thanks for the answers again! The origin of the "noise" is just the subharmonic behaviour of the converter itself (as in the case of boost converter for D>0.5). My task now is not to eliminate these phenomenon, but to study HOW subharmonic oscillations at fsw/2, fsw/4.... propogate to the output and influence output voltage ripples, knowing control-to-output transfer functions. Any suggestions?
THANKS IN ADVANCE!
 

Baseband ripple comes from the unavoidable current ripple
(VIN, L) triangle wave as filtered by the output caps. It
doesn't have to do with the control loop. But an unstable
control loop or one that is busy with subharmonic activity
can be much worse than baseband ripple.

In surrent mode control, slope compensation is needed to
quench a f/2 subharmonic at VOUT > VIN/2.

PCB and chip layout / bonding can induce subharmonic
behaviors (bistable output duty) especially if one output
edge is positioned near (esp. slightly preceding) the
SYNC pin active edge. The induced ground ringing can
couple against the input edge through input buffer ground.
 
Thanks for the help, but the question is still unclear for me. I know the sources of subharmonics and I know how to "kill" them, but my task is just to study THEIR effect on the output voltage ripples and to detect by what amount Vpp increase- analytically....
 

As has been said, the feedback loop should have no effect on output ripple so long as everything is stable (meaning no subharmonic oscillation as well). I suppose if you want to be absolutely correct, it will have some finite effect, but it should be incredibly small when compared to other contributing sources (like output capacitor ESR and ESL). And explicitly calculating the contribution would be incredibly complex, I'm sure.

If you want to calculate the effects of subharmonic oscillation on ripple, then that isn't too bad. But I've never seen equations actually defining the amplitude of subharmonic oscillations; just the conditions under which they exist.
 
Thank you for explanaiton!
Than I'll try to compute the equations myself.
 

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