Kindly find the papers attached, They are to design a LDO for memories.
You shall face some hitches, but a good one
LOW-VOLTAGE LINEAR VOLTAGE REGULATOR SUITABLE FOR MEMORIES
W. Aloisi, S.M. Billé, G. Palumbo
ABSTRACT
In this communication a low-voltage linear voltage regulator in
CMOS technology is presented. It is based on a two class-AB
gain stage and, hence, does not suffers from internal slew-rate
limitation when very large load capacitances are used. The
linear regulator suitable for memory application was designed in
a 0.35 µm standard CMOS technology. The regulator can work
with a no-regulated input voltage in the range from 1.3 V to 3 V
providing a regulated voltage of 1 V with a load capacitance of 2.2nF