Cascode transistor and it biasing can be considered as so-called "gate follower".
In the first figure, source terminal of Q4 copying the source potential of Q3, which is nothing more like Vgs of Q1=Vdsat1+Vth1. So, this cascode current source working properly as long as Vout-VS(Q4) > Vdsat4. However VS(Q4) is already equal to Vdsat1+Vth1. When we decrease the Vout below Vth+2Vdsat, cascode transistor Q4 is in linear region (as long Vout>Vgs(Q1) potential at source of Q4 is constant) and the circuit acts as simple current mirror.