Voltage degradation in Hold mode of the bootstrap switch ?

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Electric_Shock

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I have a problem with the bootstrap switch for ADC. In the sampling phase, output voltage can exactly track to the input voltage. However, when the CLK is low, the switch is off and the output voltage decreases by 3-4mV. The bigger the sampling MOS is, the higher the output voltage decreases by. Can you explain for me? Thank in advance.
 

The effect is called "hold step", happens due to switch charge injection, in other words Cgd respectively Cgs of the switch MOSFET.
 

This is charge injection and clock feedthrough. In a boot-strapped switch, this effect should be largely linear, maybe up to 10bit.
 

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