Voltage controlled delay line in verilog AMS

module vcdl ( VC, CK_IN, CK_OUT );
input VC, CK_IN; output CK_OUT;
electrical VC, CK_IN, CK_OUT;
parameter real Fref=200M from (0:inf);
parameter real Vlo=0, Vhi=1.8;
parameter real tt=50p from (0:inf);
parameter real ttol=1f from (0:(1/Fref));
parameter integer seed0=-500;
parameter real Da1=1.29e+7, Db1=-10.08,
Dc1=828.5, Dd1=-1.065;
parameter real Ja1=6.753e+10, Jb1=-17.18,
Jc1=2194, Jd1=-2.164;
real Delay,jitter, dTp, dT, vout;
integer seed;
analog begin
@(initial_step) begin
seed=seed0;
end
@(cross(V(CK_IN)-0.9,+1,ttol))begin
jitter = ( (Ja1*exp(Jb1*V(VC)))
+(Jc1*exp(Jd1*V(VC))) )*1f;
Delay = ( (Da1*exp(Db1*V(VC)))
+(Dc1*exp(Dd1*V(VC))) )*1p;
dT=jitter*$rdist_normal(seed,0,1);
dTp=dT+Delay-tt/2;
vout=Vhi;
end
@(cross(V(CK_IN)-0.9,-1,ttol))begin
jitter = ( (Ja1*exp(Jb1*V(VC)))
+(Jc1*exp(Jd1*V(VC))) )*1f;
Delay = ( (Da1*exp(Db1*V(VC)))
+(Dc1*exp(Dd1*V(VC))) )*1p;
dT=jitter*$rdist_normal(seed,0,1);
dTp=dT+Delay-tt/2;
vout=Vlo;
end
V(CK_OUT)<+ transition(vout,dTp,tt);
end

`include "constants.vams"
`include "disciplines.vams"

module vcdl_va ( VC, CK_IN , CK_OUT );

input CK_IN, VC; output CK_OUT ; electrical CK_OUT, CK_IN, VC ;

parameter real fixed_delay=50e-12;

real time_delay;

analog begin


time_delay = V(VC)*(0.1e-9)+fixed_delay;

V(CK_OUT) <+ absdelay(V(CK_IN),time_delay,{10e-9});


end

endmodule