raghuvlsi
Member level 1

Hai iam trying for job on vlsi designer as a Fresher.
i have completed my course on cadance tools
1.Encounter 6.2 version
2.STA(synopsys)
i have intresting on place&route and timing.
i have done the projects like USB Wrapper(130nm),PCI Full Chip(180nm).
and iam familier with verilog,
Perl scripting language.
if u have any references please help me.
i have completed my course on cadance tools
1.Encounter 6.2 version
2.STA(synopsys)
i have intresting on place&route and timing.
i have done the projects like USB Wrapper(130nm),PCI Full Chip(180nm).
and iam familier with verilog,
Perl scripting language.
if u have any references please help me.