vlsi chip designing.....

[Muthuraja.M]

Hi friends ,


I want to know about delay lines....


How can we develop a delay line using verilog ?...


Pls give me suggestions....


Thanks in advance....:|

 

[dillikumar406]

in verilog we can add delay by using # symbol in locking and non-blocking assignments. you can find them if you go through verilog coding books

 

[rca]

For info, the # symbol is not synthesizable.
a delay line need to be control carrefully, so you could insert the cell in the RTL code and handle to not be removed during the synthesis and placement optimisation, with SDC constrains.
And if you want delay line, I beleived you also want to control the placement and routing to have the "best" delay correlation.