vlsi chip designing.....

[Muthuraja.M]

Hi ,

Is it possible to use clock gating in combinational circuits like full adder , multiplier etc..

Pls give me the design or verilog code?

 

[chiranjeevinaidu]

Hi,
clock gating used only between two sequential circuits or latches .
main concern of clock gating circuit to reduce the dynamic power

Thanks
chiranjeevi.pandamaneni

 

[Muthuraja.M]

Thanks...

How to design a buffer . Is buffer a latch or a inverter pairs ..

pls suggest me how to use buffer in modelsim ?