vlsi chip designing........

[Muthuraja.M]

Hi guys ,

Can anyone tell the developing procedure of a digital low pass filter in verilog.

I m having idea about the design but i dont know how to start it.

Thanks in advance........

 

[sudeep_]

You can do with Verilog on Model sim/ FPGA syntthesis
or Model sim/ Synopsys Design compiler/ Cadence soc encounter

 

[Muthuraja.M]

I dont know how to start ? How to generate a random frequency of clock pulse ?

 

[sudeep_]

I dont know how to start ? How to generate a random frequency of clock pulse ?

As i know First generate the analog signal or clock pulse text file with Matlab, and read the text file in verilog or vhdl

 

[Muthuraja.M]

For example If i have generate an analog signal of Asin(2*pi*f*t)

How can i read that signal using verilog :

please clarify

 

[sudeep_]

For example If i have generate an analog signal of Asin(2*pi*f*t)

How can i read that signal using verilog :

please clarify

generate the analog signal( A sin (2*pi*f*t)) in Matlab.
Convert the matlab signal into text file.
Read the text file values in Verilog. ( you can find in google for reading file program in verilog/vhdl)

For reference read this thesis report from pgno.40. https://liu.diva-portal.org/smash/get/diva2:609369/FULLTEXT01.pdf