I commiserate with you, I've also been suffering from the lack of explanation of error/warning messages for Vivado. You probably should ask stuff like this on Xilinx's forum as factory FAE types spend time answering questions on that forum.
Have you looked at the design to see where ATA_IORDY goes? If it's used in any edge detecting code line rising_edge (ATA_IORDY) or always @(posedge ATA_IORDY) then it will be ignored for set_input_delay constraint as you would add any "offset" delays for a "clock" in the create_clock command (Yeah, I know ATA_IORDY is not actually a clock, but the original designer made it a clock ).