Sunayana Chakradhar
Member level 5
Hello All,
I have received an excel sheet from my PCB designer for ZC7020 SoC. I need to do pre synthesis pin planning for the same and check the DRC. I need to create IO ports, set IO standards and direction of the ports. I want to know 2 things.
1. I am using almost all 400 pins on the SoC. Should I manually create the IO ports?
2. There is an option in the vivado pin planning tool where in i can import IO ports in the form of a .xdc or .csv file. When I tried doing this, it will import only the site names and the bank numbers. It doesn't automatically set the IO standards nor the directions.
3. Is DRC checked only for the non PS pins (Bank 13,33,34). Bank 500, 501, 502 are the PS MIO pins and there is no user accessibility on them. They cannot be made into ports at all.
I am a little confused as i have to create IO ports manually each time. Please clarify.
I have received an excel sheet from my PCB designer for ZC7020 SoC. I need to do pre synthesis pin planning for the same and check the DRC. I need to create IO ports, set IO standards and direction of the ports. I want to know 2 things.
1. I am using almost all 400 pins on the SoC. Should I manually create the IO ports?
2. There is an option in the vivado pin planning tool where in i can import IO ports in the form of a .xdc or .csv file. When I tried doing this, it will import only the site names and the bank numbers. It doesn't automatically set the IO standards nor the directions.
3. Is DRC checked only for the non PS pins (Bank 13,33,34). Bank 500, 501, 502 are the PS MIO pins and there is no user accessibility on them. They cannot be made into ports at all.
I am a little confused as i have to create IO ports manually each time. Please clarify.