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Library UNISIM;
use UNISIM.vcomponents.all;
use work.library.all;
use work.temp_library.all;
Library XilinxCoreLib;
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component br_1_4
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(3 downto 0);
addra: IN std_logic_VECTOR(9 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(9 downto 0);
doutb: OUT std_logic_VECTOR(3 downto 0));
end component;
begin
bram_01 : entity br_1_4 port map(clka=>clk25, dina=>dataWR, addra=>adrA, wea=>WRENA( 1), clkb=>clk50, addrb=>adrB, doutb=>dataRD( 1));
bram_02 : entity br_1_4 port map(clka=>clk25, dina=>dataWR, addra=>adrA, wea=>WRENA( 2), clkb=>clk50, addrb=>adrB, doutb=>dataRD( 2));
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