wire divclk, clk_slow;
reg [26:0] divider;
// clock divider
always @(posedge clk)
divider <= divider + 1;
assign divclk = divider[17]; // divided clock for SPI controller
assign clk_slow = divider[26]; // divided clock for the counter
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets enable_IBUF] >
enable_IBUF_inst (IBUF.O) is locked to IOB_X0Y61
and enable_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
But I don't think that's what your error is. It looks like you're using a non-clock pin for your clock input.
reg clk_slow;
always @(posedge clk)
if (&(clk))
clk_slow <= 1'b1;
else
clk_slow <= 1'b0;
I'm not a Verilog guy, but that doesn't look right to me. Isn't that just going to set clk_slow high forever?
I would look at your constraints. It looks like you're trying to connect an IBUF to a BUFG. I haven't looked at the exact chip you're using, but this might be the problem. And sometimes the synthesis tool will automatically insert buffers when you don't really want them; check that.
reg [26:0] divider;
always @(posedge clk)
divider <= divider + 1;
always @(posedge clk)
if (&(divider))
clk_slow <= 1'b1;
else
clk_slow <= 1'b0;
This is very normal for Vivado to inser such BUFs.It seems that the implementation tool has really added a BUFG element after IBUF.
÷r is a reduction AND operation the result is 1'b1 only if all bits of divider are 1'b1.Can someone confirm, I'm more a VHDL monkey but in Verilog I believe ÷r is a reduction-AND operation? Therefore clk_slow is only '0' for one clk, and clk_slow is '1' for many clk's
reg [26:0] divider;
always @(posedge clk)
divider <= divider + 1;
always @(posedge clk)
if (&(divider))
clk_slow <= 1'b1;
else
clk_slow <= 1'b0;
Hi,
I'm missing a lot of informations....
* do you want to build an SPI MASTER or an SPI SLAVE?
* what is your system clock frequency?
* How many bits wide is your BCD counter?
* how wide and how deep (do you need) is your FIFO? How do you trigger input and output?
* show a drawing of your signal flow.
*****
* I don't think you need a FIFO. A simple DFF should do the job.
* with correct clock divider implementation ... there is no crossing of clock domain.
(there are many threads, documents, even video tutorials on how to correctly build a clean clock divider. There are a lot of code examples. Which one did you go through to build your code?)
With signal[26] you try to divide your system clock by 2^27.... this is about 129 million. I don't expect "a couple tens of kHz."
Klaus
Thus with counter[26] you generate a slow clock of less than 1Hz = 0.001kHz.2. My master clock frequency is 125 MHz
--> I assume you did not read through the clock dividing concept. Most (maybe all) of the circuitry needs to be driven by the 125MHz master clock. The divider just controls the "enable".all the rest of the logic is run at this clock frequency
Even 17.tap is not able to generate clocks in the 10kHz range. You should not have difficulties to calculate this...do you?The SPI clock is run from the 17. th register tap.
This is very basic stuff, thus there are many sources for the same information.Please, if you have a good link to recommend
Klaus, the clock at 26th tap should be 125MHz/2^26 what is roughly 1.9Hz. The counter updates every clock strike, so transmitting the 16 digits data through parallel interface to the FIFO is at 1.9Hz and not every 16 seconds.Hi,
Thus with counter[26] you generate a slow clock of less than 1Hz = 0.001kHz.
--> It takes at least 16 seconds to transmit your 4 digits data.
Please find attached the full concept what I am trying to do. The SPI interface along with the finite state machine works fine. I tested sending commands to MAX7219 turning the LED display on and showing a couple numbers.4) --> show a drawing of what you want to do.
5) --> it is 4 sample deep.... I assume it is 16 bits wide. Please confirm, or show it in the drawing.
Not yet, I am still looking for an appropriate article.--> I assume you did not read through the clock dividing concept. Most (maybe all) of the circuitry needs to be driven by the 125MHz master clock. The divider just controls the "enable".
Again: a drawing of your concept should clarify...
Sorry for my non-consistent calculations, it should be around 950 kHz in this case. However, this works just fine, since it is within timing specs of MAX7219.6)
Even 17.tap is not able to generate clocks in the 10kHz range. You should not have difficulties to calculate this...do you?
This is very basic stuff, thus there are many sources for the same information.
I recommend to go to the FPGA manufacturer's internet site.
Don't rely on random people's information. Look for FPGA manufacturers, HDL tools manufacturers, universities....they are reliable.
And they even provide videos and code examples
Klaus
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