mselmanerel
Newbie level 1
Hi guys,
I am Selman, Graduate Student in Electrical Engineering Department in Bilkent University,Ankara, Turkey. My professor gave me a project which is generating 500Hz from 125 KHz built-in FGPA oscillator. I have code something in VHDL and it is correct in a syntax manner. However, when it is come to generate bitstream, Vivado did not generate bitstream instead, it gave an error named "[DRC 23-20] Rule violation (LUTLP-1) Combinatorial Loop". I could not find anything leads to combinatorial loop. Code is rather simple, I am a newbie VHDL coder. VHDL code and constraint code is attached to the message. If you help me, I will be rather happy. Best Regards,
I am Selman, Graduate Student in Electrical Engineering Department in Bilkent University,Ankara, Turkey. My professor gave me a project which is generating 500Hz from 125 KHz built-in FGPA oscillator. I have code something in VHDL and it is correct in a syntax manner. However, when it is come to generate bitstream, Vivado did not generate bitstream instead, it gave an error named "[DRC 23-20] Rule violation (LUTLP-1) Combinatorial Loop". I could not find anything leads to combinatorial loop. Code is rather simple, I am a newbie VHDL coder. VHDL code and constraint code is attached to the message. If you help me, I will be rather happy. Best Regards,