Regarding constraints inside verilog code (as opposed to ucf/xdc files), how does Vivado handle that? In ISE it worked, but there were some sneaky gotcha's. Is Vivado better in this regard than ISE? Worse? About the same, including same sh!t as usual complete with gotcha's?
I mean the type of constraints where you for example specify an RLOC or BEL for a flip-flop.
And in ISE there were also types of constraints that would silently fail (raaaawr), so you would think they applied but nooooope. And then you specified the exact same constraint in an UCF entry and that would suddenly be totally acceptable, and give the expected result.