Vivado and inline constraints in verilog.

[mrflibble]

Regarding constraints inside verilog code (as opposed to ucf/xdc files), how does Vivado handle that? In ISE it worked, but there were some sneaky gotcha's. Is Vivado better in this regard than ISE? Worse? About the same, including same sh!t as usual complete with gotcha's?

I mean the type of constraints where you for example specify an RLOC or BEL for a flip-flop.

---

Code Verilog - [expand]
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(* RLOC=X0Y0 *) reg obligatory_flipflop;
(* RLOC=X1Y0 *) reg this_calls_for_another_flipflop;
 
always @(posedge clk) begin
    obligatory_flipflop <= ~obligatory_flipflop;
    this_calls_for_another_flipflop <= ~this_calls_for_another_flipflop;
end

---

And in ISE there were also types of constraints that would silently fail (raaaawr), so you would think they applied but nooooope. And then you specified the exact same constraint in an UCF entry and that would suddenly be totally acceptable, and give the expected result.

So I was wondering how this is in Vivado?

 

[ads-ee]

I haven't used location constraints, but I know that the following worked without problems:

(* dont_touch = "true" *)
(* mark_debug = "true" *)
(* iob = "false" *)
(* shreg_extract = "no" *)
(* async_reg = "true" *)

 

[mrflibble]

http://www.xilinx.com/support/answers/54699.html

Good to know that dont_touch works. Because some of the issues in ISE I mentioned were related to SAVE / KEEP flags.