When you analyse DC steady state circuit, you can see capacitor as an open circuit, but in the integrator with the OP-amp RC circuit not steady.
In the integrator with the OP-amp RC (in your figure node 1 5 6), Vs = DC voltage, if at t=0 voltage across the capacitor is 0, OP-amp is ideal so pin + and pin - are the same voltage (ground in this situation). There is a current flow form Vs to node 5 (with value is Vs/R2), because input current of ideal OP-amp equal to zero so this current will flow to capacitor make it voltage increase. When t increase, t>0, the voltage of capacitor increase (because input current of OP-amp is always equal to zero) so the circuit'state is not steady state so we can't see the capacitor is an open circuit to analyse in this situation. To analyse this circuit accurately in this situation, we can see OP-amp is ideal and use KCL and KVL to find current and voltage. If you afraid that we use ideal OP-amp to solve there is not accurate you can use its linear model (because in this circuit we use OP-amp ' linearity) with input resistor and voltage gain is very large.
This is my opinion. Hope it helpful.